Patents by Inventor Michael J. Becht
Michael J. Becht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11061701Abstract: Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.Type: GrantFiled: September 25, 2019Date of Patent: July 13, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Becht, Raymond Wong
-
Patent number: 10691519Abstract: Examples of techniques for hang detection and recovery are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: sending, by a processor, a read request to a controller; detecting, by a data hang detection circuit, the read request; initiating, by the data hang detection circuit, a counter when the read request is first detected; monitoring, by the data hang detection circuit, to receive a read response from the controller; and responsive to the counter reaching a timeout threshold before receiving the read response, sending, by the data hang detection circuit a timeout error to the processor via a multiplexer in the data hang detection circuit.Type: GrantFiled: September 15, 2016Date of Patent: June 23, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Becht, Yuen C. Tschang, Raymond Wong, Jie Zheng
-
Patent number: 10558477Abstract: Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.Type: GrantFiled: November 16, 2016Date of Patent: February 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Becht, Raymond Wong
-
Patent number: 10552184Abstract: Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.Type: GrantFiled: February 23, 2017Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Becht, Raymond Wong
-
Publication number: 20200019422Abstract: Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Inventors: Michael J. Becht, Raymond Wong
-
Publication number: 20180136690Abstract: Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.Type: ApplicationFiled: February 23, 2017Publication date: May 17, 2018Inventors: Michael J. Becht, Raymond Wong
-
Publication number: 20180136689Abstract: Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.Type: ApplicationFiled: November 16, 2016Publication date: May 17, 2018Inventors: Michael J. Becht, Raymond Wong
-
Publication number: 20180074875Abstract: Examples of techniques for hang detection and recovery are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: sending, by a processor, a read request to a controller; detecting, by a data hang detection circuit, the read request; initiating, by the data hang detection circuit, a counter when the read request is first detected; monitoring, by the data hang detection circuit, to receive a read response from the controller; and responsive to the counter reaching a timeout threshold before receiving the read response, sending, by the data hang detection circuit a timeout error to the processor via a multiplexer in the data hang detection circuit.Type: ApplicationFiled: September 15, 2016Publication date: March 15, 2018Inventors: Michael J. Becht, Yuen C. Tschang, Raymond Wong, Jie Zheng
-
Patent number: 9792167Abstract: Examples of techniques for transparent north port recovery of an error in an input/output device are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processing device, a command timeout; sending, by the processing device, an input/output (I/O) error signal to a host processing system connected to the hardware device via a north port of the hardware device; terminating, by the host processing system, a link between the north port of the hardware device and the host processing system; enabling, by the processing device, halt command forwarding on the hardware device; halting, by the processing device, commands upon detecting the halt command forwarding; and resetting, by the processing device, the link between the north port of the hardware device and the host processing system.Type: GrantFiled: September 27, 2016Date of Patent: October 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Becht, Clinton E. Bubb, Jeffrey C. Hanscom, Andreas Kohler, Ying-Yeung Li, Mushfiq U. Saleheen, Raymond Wong, Jie Zheng