Abstract: A method and apparatus for controlling data flow across a network performs a method which includes transmitting a packet request message from a first station to a second station, then determining if the packet request message is valid. A request acknowledge message is transmitted from the second station to the first station, and it is then determined if the request acknowledge message is valid. The packet request message and the request acknowledge message each includes a control bit string, an identification bit string, and at least one parity bit.

Abstract: A network device for processing packets. The network device includes an ingress module for performing switching functions on an incoming packet. The network device also includes a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting the packet to an appropriate destination port. Each of the ingress module, memory management unit and egress module includes multiple cycles for processing instructions and each of the ingress module, memory management unit and egress module processes one packet every clock cycle.

Abstract: A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

Abstract: A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

Abstract: A method and apparatus for controlling data flow across a network performs a method which includes transmitting a packet request message from a first station to a second station, then determining if the packet request message is valid. A request acknowledge message is transmitted from the second station to the first station, and it is then determined if the request acknowledge message is valid. The packet request message and the request acknowledge message each includes a control bit string, an identification bit string, and at least one parity bit.

Abstract: A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

Abstract: A method and apparatus for controlling data flow across a network performs a method which includes transmitting a packet request message from a first station to a second station, then determining if the packet request message is valid. A request acknowledge message is transmitted from the second station to the first station, and it is then determined if the request acknowledge message is valid. The packet request message and the request acknowledge message each includes a control bit string, an identification bit string, and at least one parity bit.

Abstract: A network switch for switching packets from a source to a destination includes a source port for receiving an incoming packet from a source, a destination port which contains a path to a destination for the packet, and a filter unit for constructing and applying a filter to selected fields of the incoming packet. The filter unit further includes filtering logic for selecting desired fields of the incoming packet and copying selected field information therefrom. The filtering logic also constructs a field value based upon the selected fields, and applies a plurality stored field masks on the field value. The switch additionally includes a rules table which contains a plurality of rules therein. The filtering logic is configured to perform lookups of the rules table in order to determine actions which must be taken based upon the result of a comparison between the field value and the stored filter masks and the rules table lookup.

Abstract: A network switch having an internet port interface controller, includes a high performance interface for communicating with other switches and components through the transfer of data packets contained in memory. The high performance interface includes a data connection bus, where data is transferred on both a rising edge and a falling edge of a clock signal, and the data connection bus has output drivers and a multiplexing circuit connected to the output drivers. The multiplexing circuit is constructed through two levels of glitchless multiplexors, to serialize said data transmitted over said high performance interface. Because two levels of glitchless multiplexors are employed, function hazards that occur in the glitchless multiplexors when more than one input thereto change simultaneously can be masked, and do not create noise that can be propagated to an output driver.

Abstract: A direct memory access (DMA) controller is connected to the CPU bus of a computer system through a bus interface and is also connected to an I/O bus, which is coupled to one or more I/O controllers. Multiple channels, each corresponding to a particular I/O controller, are contained within the DMA controller. The DMA controller controls DMA transfers between the I/O controllers and the main memory of the system and allows multiple transfers to occur concurrently. The DMA controller controls transfers in part through a first arbiter which arbitrates requests for access to the CPU bus coming from the DMA channels and a second arbiter which arbitrates requests for access to the I/O bus coming from the DMA channels and the CPU.

Abstract: An ethernet receive channel, corresponding to an ethernet controller, is contained within a direct memory access (DMA) controller. The DMA controller is connected to the CPU bus of a computer system through a bus interface and is also connected to an I/O bus, which is coupled to one or more I/O controllers, including an ethernet controller. The ethernet receive channel contains a buffer and multiple register sets storing the number of packets to be received for a particular DMA transfer, the address where the next byte of the incoming ethernet packet will be written in memory, and control information for the transfer. The address registers are initially programmed with the starting location for the transfer in main memory, which correspond to segments within chains of contiguous physical memory. During a transfer, the address registers are updated to contain the location where the next portion of the incoming ethernet packet will be written in memory.

Abstract: A direct memory access (DMA) controller is connected with the CPU bus of a computer system through a bus interface and also to an I/O bus, which is connectable to one or more I/O controllers. The DMA controller contains multiple channels, each corresponding to a particular I/O controller, which are coupled to both the bus interface and the I/O bus. Each of the channels contains at least one register set storing information for the transfer and a data buffer holding the data during a transfer between the I/O bus and the CPU bus.

Abstract: An arbitration scheme for a computer system in which a digital signal processor resides on the computer system's memory bus without requiring a block of dedicated static random access memory. An arbitration cycle is divided into 10 slices of which 5 slices are provided in each arbitration loop to the digital signal processor. Two slices are provided each to the system's I/O interface and to the peripheral bus controller. A final slice is provided to the system's CPU. A default state when no memory bus resource is requesting the system memory bus parks the memory bus on the CPU. The arbitration scheme provides sufficient bandwidth for real-time signal processing by the digital signal processor operating from the system's dynamic random access memory while also providing sufficient bandwidth for a local area network interface through the system's I/O interface.