Abstract: A clock signal generator comprises a clock input CK and N stages where N is greater than three. Each of the stages comprises a transmission gate M3, M4 which passes clock pulses from the clock Input CK in response to a control signal a from the preceding stage. A control signal generating circuit M5, M6, D7, M8 supplies a control signal e to the succeeding stage when the control signal a from the preceding stage and the clock pulse from the transmission gate M3, M4 have ended. The control signal generating circuit M5, M6, D7, M8 ends the control signal e when the succeeding stage produces its control signal F.

Abstract: A clock pulse generator comprises N stages 1, 2, where N is greater than 3. Each ith stage comprises a transmission gate M3, M4; M9, M10 which is controlled by a control signal from the (i−1)th stage for passing a clock pulse from the clock input CK to the output Nn, Pp of the stage. A control signal generating circuits M5, M6; M11, M12 supplies a control signal to the (i+1)th stage and is inhibited from supplying further control signals in response to a control signal from the (i+2)th stage, where 1<i<(N−1).