Patents by Inventor Michael J. Craren
Michael J. Craren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8762581Abstract: A multi-thread packet processor which processes data packets using a multi-threaded pipelined machine, wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.Type: GrantFiled: December 22, 2000Date of Patent: June 24, 2014Assignee: Avaya Inc.Inventors: Richard P. Modelski, Michael J. Craren
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Patent number: 7369554Abstract: A method performs a plurality of filter operations on a data packet using an instruction. The method receives an instruction to filter at least one data packet. The method retrieves a filter result based on the received instruction. The method then performs a plurality of filter operations on the at least one data packet in accordance with the retrieved filter result.Type: GrantFiled: December 22, 2000Date of Patent: May 6, 2008Assignee: Nortel Networks LimitedInventors: Richard P. Modelski, Adrian M. Kristiansen, Michael J. Craren
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Patent number: 7283747Abstract: An optical switch router performs both optical switching and traditional routing. The optical switch router includes optical interfaces for coupling to one or more incoming optical fibers and to one or more outgoing optical fibers, and also includes a number of traditional router ports. Individual incoming optical data streams received over the incoming optical fiber(s) can be selectively passed through to one or more of the outgoing optical fibers or “dropped” from the optical communication path for traditional routing. Routed traffic, which can be received over the router ports or from the “dropped” optical data streams, can be forwarded over optical data streams that are “added” to the outgoing optical fiber(s). The “added” optical data streams may be added to the outgoing optical fiber(s) at any unused wavelengths, including, but not limited to, the wavelengths of the “dropped” optical data streams.Type: GrantFiled: August 15, 2001Date of Patent: October 16, 2007Assignee: Nortel Networks LimitedInventors: Bruce A. Schofield, James V. Luciani, Michael J. Craren
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Patent number: 7131125Abstract: Route switch packet architecture processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The route switch packet architecture includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.Type: GrantFiled: December 22, 2000Date of Patent: October 31, 2006Assignee: Nortel Networks LimitedInventors: Richard P. Modelski, Michael J. Craren
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Patent number: 7069422Abstract: A shift left with carry instruction minimizes the number of instructions required for implementing a binary search. A multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator, wherein the analysis machine implements a binary search by executing a shift left with carry instruction to minimize the number of instructions required for the binary search. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.Type: GrantFiled: December 22, 2000Date of Patent: June 27, 2006Inventors: Richard P. Modelski, Michael J. Craren
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Patent number: 7039627Abstract: A method performs a radix search data structure. The method selects a reference table based on a value of a selectable parameter. The reference table includes at least one of a valid reference table and a transition reference table, and contains a set of data bits. The method receives a key containing a set of data bits. The method indexes the reference table using at least a subset of data bits in the key. The method determines a result index based on at least a subset of data bits in the reference table. The method then indexes a result table based on the result index to reference a result of a radix search data structure.Type: GrantFiled: December 22, 2000Date of Patent: May 2, 2006Assignee: Nortel Networks LimitedInventors: Richard P. Modelski, Michael J. Craren, Adrian M. Kristiansen, Richard L. Angle, Geoff B. Ladwig
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Patent number: 7013302Abstract: A bit field direct manipulation device which processes data packets using a multi-threaded pipelined machine, wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.Type: GrantFiled: December 22, 2000Date of Patent: March 14, 2006Assignee: Nortel Networks LimitedInventors: Richard P. Modelski, Michael J. Craren
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Patent number: 6981077Abstract: Global access bus architecture includes a master request bus and a slave request bus separated from each other and pipelined. The global access bus architecture includes packet input global access bus software code for flow of data packet information from a flexible input data buffer to an analysis machine, packet data global access bus software code for flow of packet data between a flexible data input bus and a packet manipulator, statistics data global access bus software code for connection of an analysis machine to a packet manipulator, private data global access bus software code for connection of an analysis machine to an internal memory engine, lookup global access bus software code for connection of an analysis machine to an internal memory engine, results global access bus software code for providing flexible access to an external memory, and results global access bus software code for providing flexible access to an external memory.Type: GrantFiled: December 22, 2000Date of Patent: December 27, 2005Assignee: Nortel Networks LimitedInventors: Richard P. Modelski, Michael J. Craren
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Patent number: 6934780Abstract: An external memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator.Type: GrantFiled: October 3, 2003Date of Patent: August 23, 2005Assignee: Nortel Networks LimitedInventors: Richard P. Modelski, Michael J. Craren, Adrian M. Kristiansen
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Patent number: 6665755Abstract: External memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator.Type: GrantFiled: December 22, 2000Date of Patent: December 16, 2003Assignee: Nortel Networks LimitedInventors: Richard P. Modelski, Michael J. Craren, Adrian M. Kristiansen
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Patent number: 6633880Abstract: A method performs a radix search data structure. The method receives a key containing a set of data bits. The method determines a reference index based on a first subset of data bits in the key. The method indexes a reference table based on the reference index to locate a reference field. The method determines a result index based on a second subset of data bits in the key and the reference field. The method then indexes a result table based on the result index to locate a result of a radix search data structure.Type: GrantFiled: December 22, 2000Date of Patent: October 14, 2003Assignee: Nortel Networks LimitedInventors: Richard P. Modelski, Michael J. Craren, Adrian M. Kristiansen, Richard L. Angle, Geoff B. Ladwig
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Publication number: 20020120828Abstract: A bit field direct manipulation device which processes data packets using a multi-threaded pipelined machine, wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.Type: ApplicationFiled: December 22, 2000Publication date: August 29, 2002Inventors: Richard P. Modelski, Michael J. Craren
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Publication number: 20020120798Abstract: Global access bus architecture includes a master request bus and a slave request bus separated from each other and pipelined. The global access bus architecture includes packet input global access bus software code for flow of data packet information from a flexible input data buffer to an analysis machine, packet data global access bus software code for flow of packet data between a flexible data input bus and a packet manipulator, statistics data global access bus software code for connection of an analysis machine to a packet manipulator, private data global access bus software code for connection of an analysis machine to an internal memory engine, lookup global access bus software code for connection of an analysis machine to an internal memory engine, results global access bus software code for providing flexible access to an external memory, and results global access bus software code for providing flexible access to an external memory.Type: ApplicationFiled: December 22, 2000Publication date: August 29, 2002Inventors: Richard P. Modelski, Michael J. Craren
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Publication number: 20020116442Abstract: Route switch packet architecture processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The route switch packet architecture includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.Type: ApplicationFiled: December 22, 2000Publication date: August 22, 2002Inventors: Richard P. Modelski, Michael J. Craren
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Publication number: 20020116449Abstract: A shift left with carry instruction minimizes the number of instructions required for implementing a binary search. A multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator, wherein the analysis machine implements a binary search by executing a shift left with carry instruction to minimize the number of instructions required for the binary search. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.Type: ApplicationFiled: December 22, 2000Publication date: August 22, 2002Inventors: Richard P. Modelski, Michael J. Craren
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Publication number: 20020116587Abstract: External memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator.Type: ApplicationFiled: December 22, 2000Publication date: August 22, 2002Inventors: Richard P. Modelski, Michael J. Craren, Adrian M. Kristiansen
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Publication number: 20020083297Abstract: A multi-thread packet processor which processes data packets using a multi-threaded pipelined machine, wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.Type: ApplicationFiled: December 22, 2000Publication date: June 27, 2002Inventors: Richard P. Modelski, Michael J. Craren