Abstract: Test benches, simulations, and scripts are invoked in parallel for testing multiple points in a circuit being synthesized in an Analog Mixed Signal environment. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis uses a set of design parameters. At least one circuit model is used to incorporate the set of design parameters, each circuit model adapted to model a portion of the circuit pertaining to a performance characteristic. At least one analysis test bench is then connected to each circuit model. Each analysis test bench is adapted to model circuitry external to the circuit and control the type of analysis to be performed for each performance characteristic of the circuit.

Abstract: Circuit synthesis is performed utilizing an optimizer that selects design parameters for a synthesis model of a circuit based on desired performance characteristics and performance characteristics/design parameters of previously synthesized circuits. Performance characteristics and design parameters of each synthesized circuit are maintain in conjunction with the synthesis model of the circuit being synthesized. A synthesis plan identifies the synthesis model and specific instructions on how to perform optimized selection of design parameters, how to set up test benches, and how to perform the simulation.

Abstract: Method and apparatus for the synthesis of electronic circuits and, more particuarly, to the synthesis of analog circuitry and mixed digital and analog circuitry, and related to the reuse of circuit designer knowledge for the simulation of mixed analog and digital circuitry to determine data points and to curve fit the data points to determine a polynomial equation that closely approximates simulated circuit performance, and related to the parameterization of circuit features with respect to circuit performance.

Abstract: Test benches, simulations, and scripts are invoked in parallel for testing multiple points in a circuit being synthesized in an Analog Mixed Signal environment. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis uses a set of design parameters. At least one circuit model is used to incorporate the set of design parameters, each circuit model adapted to model a portion of the circuit pertaining to a performance characteristic. At least one analysis test bench is then connected to each circuit model. Each analysis test bench is adapted to model circuitry external to the circuit and control the type of analysis to be performed for each performance characteristic of the circuit.

Abstract: A method and apparatus for the synthesis of electronic circuits is described herein. More particularly, the system supports the synthesis of both analog-only, and mixed digital/analog circuitry. The circuit designers knowledge is reused to effect the simulation of mixed analog and digital circuitry, determining data points and curve-fitting the data points to determine a model that closely approximates the simulated circuit performance. The model describes the parameterization of circuit features with respect to circuit performance. The parameterization is used to develop a behavioral model of the circuit that does not retain any of the physical description of the circuit.

Abstract: A Language Controlled Design Flow for the development of integrated circuits (IC) that allows users to Characterize, Synthesize, Simulate, and Analyze IC designs. The Language Controlled Design Flow provides specialized features that enable rapid design development and Intellectual Property (IP) reuse. The language provides the ability to capture a designer's knowledge about the Design Components and Design Processes unique to those components during characterization, synthesis, simulation, and analysis. A feature of this invention is the ability to separate design or design component specific knowledge from the tools used for analysis. This leads to benefits in extensibility, simplicity, accuracy, and performance of the overall tool set. Also provided is a mechanism in which the design process can be fully automated with a Language Controlled Design Flow that can take advantage of the information available in the design, in the design components, and in the design process flow.

Abstract: Auto-zeroing clocking signals, a first auto-zeroing clocking signal of comparatively-low frequency and duty cycle and a second auto-zeroing clocking signal of the same comparatively-low frequency but complementary and comparatively-high duty cycle, and a sampling clocking signal of comparatively-high frequency respectively initiate auto-zeroing of a circuit element subject to output offset error and data sampling of an A.C. input signal to a latch. The sampling of the A.C. input signal to the latch occurs at the comparatively-high frequency of the clocking signal during the "on" time of the comparatively-high duty cycle second auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide higher speed sampling than heretofore possible.

Abstract: A high-accuracy MOSFET-switched sampling circuit feeds charge feedthrough error to a load as well as to a dummy load during DC input signal sampling by a switching MOSFET, thereby reducing storage of the charge feedthrough error on the load to the extent that the charge feedthrough error is rather stored on the dummy load. During AC input signal sampling, the high-accuracy MOSFET-switched sampling circuit isolates the AC input signal from the dummy load. Charge feedthrough error produced by an isolating MOSFET that isolates the AC input signal from the dummy load is exactly compensated by a phase-opposed compensating MOSFET positioned in the DC input signal path. The dummy load and the load may be active as well as passive and may be selected to have equal and unequal electrical characteristics.

Abstract: The voltage comparator includes a first and a second voltage supply terminal, and a first and a second output node. A first current source is connected between the first supply terminal and the first output node. A first field effect transistor of one channel conductivity type is connected between the first output node and the second supply terminal. The gate of the first transistor is connected to the second output node. A second current source is connected between the first supply terminal and the second output node. A second field effect transistor of the one conductivity is connected between the second output node and the second supply terminal. The gate of the second transistor is connected to the first output node. During a first period of time the first and second output nodes and the capacitances of the gates of the first and second transistors connected thereto are maintained at the potential of the second supply terminal by switches connected thereacross.