Abstract: A display device may reduce the latency of the display of a digital signal by reducing the latency that the display device adds to the digital signal. After a digital signal is received by an input module, the signal is stored in a frame buffer as a plurality of pixels. A controller determines the input frame rate of the digital signal and a pixel delay. The controller monitors the frame buffer to determine when the frame buffer has stored a number of pixels greater than or equal to the pixel delay. After the frame buffer contains enough pixels, the controller initiates transmission of the pixels from the frame buffer to a display module. In certain embodiments, the controller initiates transmission of the pixels to the display module before the frame buffer has stored all pixels corresponding to the frame.

Abstract: A system for enhancing eye gaze in a telepresence system includes a plurality of local cameras coupled to at least one local display. Each local camera is directed to at least one respective local user section and operable to generate an image of the respective local user section. The system also includes a plurality of remote displays. Each remote display is operable to reproduce the local video image of the local user section. Within the system the plurality of remote displays and the plurality of local cameras are aligned such that when a first local user within a local user section looks at a target at least one remote display is operable to reproduce the local video image of the first user section comprising the first local user such that the eye gaze of the reproduced image of the first local user is directed approximately at a corresponding target.

Abstract: A system for enhancing eye gaze in a telepresence system includes a plurality of local cameras coupled to at least one local display. Each local camera is directed to at least one respective local user section and operable to generate an image of the respective local user section. The system also includes a plurality of remote displays. Each remote display is operable to reproduce the local video image of the local user section. Within the system the plurality of remote displays and the plurality of local cameras are aligned such that when a first local user within a local user section looks at a target at least one remote display is operable to reproduce the local video image of the first user section comprising the first local user such that the eye gaze of the reproduced image of the first local user is directed approximately at a corresponding target.

Abstract: A system and method are provided for capturing and transmitting frames in a video conference. The method comprises determining a frame rate and a shutter speed according to variable control data, capturing image data according to the determined shutter speed, and transmitting the captured image data through a communication interface to a remote video conference system. The variable control data specifies a relationship between the frame rate and the shutter speed.

Abstract: A system for enhancing eye gaze in a telepresence system includes a plurality of local cameras coupled to at least one local display. Each local camera is directed to at least one respective local user section and operable to generate an image of the respective local user section. The system also includes a plurality of remote displays. Each remote display is operable to reproduce the local video image of the local user section. Within the system the plurality of remote displays and the plurality of local cameras are aligned such that when a first local user within a local user section looks at a target at least one remote display is operable to reproduce the local video image of the first user section comprising the first local user such that the eye gaze of the reproduced image of the first local user is directed approximately at a corresponding target.

Abstract: A novel circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

Abstract: A system for enhancing eye gaze in a telepresence system includes a plurality of local cameras coupled to at least one local display. Each local camera is directed to at least one respective local user section and operable to generate an image of the respective local user section. The system also includes a plurality of remote displays. Each remote display is operable to reproduce the local video image of the local user section. Within the system the plurality of remote displays and the plurality of local cameras are aligned such that when a first local user within a local user section looks at a target at least one remote display is operable to reproduce the local video image of the first user section comprising the first local user such that the eye gaze of the reproduced image of the first local user is directed approximately at a corresponding target.

Abstract: A system and method are provided for capturing and transmitting frames in a video conference. The method comprises determining a frame rate and a shutter speed according to variable control data, capturing image data according to the determined shutter speed, and transmitting the captured image data through a communication interface to a remote video conference system. The variable control data specifies a relationship between the frame rate and the shutter speed.

Abstract: A display device may reduce the latency of the display of a digital signal by reducing the latency that the display device adds to the digital signal. After a digital signal is received by an input module, the signal is stored in a frame buffer as a plurality of pixels. A controller determines the input frame rate of the digital signal and a pixel delay. The controller monitors the frame buffer to determine when the frame buffer has stored a number of pixels greater than or equal to the pixel delay. After the frame buffer contains enough pixels, the controller initiates transmission of the pixels from the frame buffer to a display module. In certain embodiments, the controller initiates transmission of the pixels to the display module before the frame buffer has stored all pixels corresponding to the frame.

Abstract: A novel a circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment, the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

Abstract: A novel a circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment, the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

Abstract: A novel a circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment, the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

Abstract: A sleep mode controller, useful for an electronic device such as a computer, can supply multiple clocks with appropriate synchronization and which is capable of dynamic speed switching. The device provides clock signals at various speeds and relationships which can in turn be used to support various functions of the electronic device. The sleep mode controller can be activated and smoothly transition various clock signals from one time domain to a second time domain, each of which has predetermined speeds and clock-signal relationships. Dynamic speed switching is used to reset timing (bus and processor clock) sensitive elements such that computer machine speed (bus and processor clock frequencies) can be changed dynamically without interruption of I/O services or general OS and application level functions.

Abstract: A signal delay apparatus delivers synchronous signals over long and short traces. For a signal that needs to be delayed because it will be carried on a relatively short trace, passing the signal through a clocked device such as a flip flop will delay the output by a selected number of clocks. If a relatively longer trace is longer than the shorter trace by the distance a signal travels during the selected number of clock cycles, then clock signals over the respective paths will be synchronized. In a preferred embodiment, the signals are clock signals from a clock generator.

Abstract: Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches.

Abstract: Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches.

Abstract: A system in which line reflections in a clock distribution network are cancelled by providing the clock distribution network with a branching point and suitably arranging recipient devices with respect to the branching point to provide for clock pulse reflection cancellation and attenuation. Moreover, the system can be arranged so that clock pulse reflections are not received as pulses which are discrete from legitimate clock pulses. The system also provides capability for reducing electromagnetic interference.

Abstract: Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches.

Abstract: The present invention facilitates the Dynamic Random Access Memory (DRAM) refresh function in a less obtrusive manner than in the prior art. The present invention facilitates the refresh function during idle time when the DRAM is not busy handling read or write transactions. If insufficient idle time exists then the present invention will force a refresh operation thus ensuring that all memory cells are maintained in a properly charged state.

Abstract: The present invention selectively switches between two or more input signals while avoiding invalid output conditions, large power draws, and the resulting electromagnetic interference caused thereby. The present invention can be used to select between Dynamic Random Access Memory device column addresses and Dynamic Random Access Memory device row addresses.