Patents by Inventor Michael J. Ferrazano

Michael J. Ferrazano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6265895
    Abstract: The invention relates to an integrated circuit that incorporates a memory efficient interconnection device. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). By using the memory efficient interconnection device, the invention is able to reduce the quantity of memory resources required to program the interconnection device while at the same time not substantially sacrificing the probability of fitting logic functions in the CPLD. The reduction in memory resources that the CPLD must provide leads to increased availability of precious die area for other components of the CPLD.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: July 24, 2001
    Assignee: Altera Corporation
    Inventors: James Schleicher, Michael J. Ferrazano
  • Patent number: 6057707
    Abstract: The invention relates to an integrated circuit that incorporates a memory efficient interconnection device. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). By using the memory efficient interconnection device, the invention is able to reduce the quantity of memory resources required to program the interconnection device while at the same time not substantially sacrificing the probability of fitting logic functions in the CPLD. The reduction in memory resources that the CPLD must provide leads to increased availability of precious die area for other components of the CPLD.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: May 2, 2000
    Assignee: Altera Corporation
    Inventors: James Schleicher, Michael J. Ferrazano