Abstract: Disclosed herein include methods, compositions, and kits suitable for robust and tunable control of payload gene expression. Some embodiments provide rationally designed circuits, including miRNA-level and/or protein-level incoherent feed-forward loop circuits, that maintain the expression of a payload at an efficacious level. The circuit can comprise a promoter operably linked to a polynucleotide encoding a fusion protein comprising a payload protein, a protease, and one or more self-cleaving peptide sequences. The payload protein can comprise a degron and a cut site the protease is capable of cutting to expose the degron. The circuit can comprise a promoter operably linked to a polynucleotide comprising a payload gene, a silencer effector cassette, and one or more silencer effector binding sequences.

Abstract: The present disclosure relates to integrated circuits which include various structural elements. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate.

Abstract: Disclosed herein include methods, compositions, and kits suitable for use in tuned dosage-invariant expression of a payload protein. Compositions (e.g., nucleic acid compositions, one or more cells) provided herein can comprise a first promoter sequence operably linked to a first polynucleotide comprising one or more miRNA cassettes, and a second promoter sequence operably linked to a second polynucleotide comprising a payload gene. In some embodiments, the first promoter sequence is capable of inducing transcription of the first polynucleotide to generate a first transcript, and the first transcript is capable of being processed to generate said miRNA. The payload gene can comprise a miRNA target region comprising one or more miRNA target sequences.

Abstract: Disclosed herein include methods, compositions, and kits suitable for robust and tunable control of payload gene expression. Some embodiments provide rationally designed circuits, including miRNA-level and/or protein-level incoherent feed-forward loop circuits, that maintain the expression of a payload at an efficacious level. The circuit can comprise a promoter operably linked to a polynucleotide encoding a fusion protein comprising a payload protein, a protease, and one or more self-cleaving peptide sequences. The payload protein can comprise a degron and a cut site the protease is capable of cutting to expose the degron. The circuit can comprise a promoter operably linked to a polynucleotide comprising a payload gene, a silencer effector cassette, and one or more silencer effector binding sequences.

Abstract: Disclosed herein include methods, compositions, and kits suitable for use in signal amplification. There are provided, in some embodiments, protease-based signal amplification modules. Disclosed herein include amplifier proteins comprising a first part of a first protease domain, a first dimerization domain, a first cut site a protease in a protease active state is capable of cutting, a second dimerization domain, a second cut site a protease in a protease active state is capable of cutting, and a first caging domain. Disclosed herein include companion amplifier proteins comprising a second part of a first protease domain, a third dimerization domain, a third cut site a protease in a protease active state is capable of cutting, a fourth dimerization domain, a fourth cut site a protease in a protease active state is capable of cutting, and a second caging domain.

Abstract: Disclosed herein include methods, compositions, and kits suitable for robust and tunable control of payload gene expression. Some embodiments provide rationally designed circuits, including miRNA-level and/or protein-level incoherent feed-forward loop circuits, that maintain the expression of a payload at an efficacious level. The circuit can comprise a promoter operably linked to a polynucleotide encoding a fusion protein comprising a payload protein, a protease, and one or more self-cleaving peptide sequences. The payload protein can comprise a degron and a cut site the protease is capable of cutting to expose the degron. The circuit can comprise a promoter operably linked to a polynucleotide comprising a payload gene, a silencer effector cassette, and one or more silencer effector binding sequences.

Abstract: The present disclosure relates to integrated circuits which include various structural elements designed to reduce the impact of strain on the electronic components of the circuit. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate. By including such mechanical elements, variation in the electrical characteristics of the integrated circuit are reduced.

Abstract: The present disclosure relates to integrated circuits which include various structural elements designed to reduce the impact of strain on the electronic components of the circuit. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate. By including such mechanical elements, variation in the electrical characteristics of the integrated circuit are reduced.

Abstract: A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

Abstract: The present disclosure relates to integrated circuits which include various structural elements designed to reduce the impact of strain on the electronic components of the circuit. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate. By including such mechanical elements, variation in the electrical characteristics of the integrated circuit are reduced.

Abstract: Disclosed herein include methods, compositions, and kits suitable for robust and tunable control of payload gene expression. Some embodiments provide rationally designed circuits, including miRNA-level and/or protein-level incoherent feed-forward loop circuits, that maintain the expression of a payload at an efficacious level. The circuit can comprise a promoter operably linked to a polynucleotide encoding a fusion protein comprising a payload protein, a protease, and one or more self-cleaving peptide sequences. The payload protein can comprise a degron and a cut site the protease is capable of cutting to expose the degron. The circuit can comprise a promoter operably linked to a polynucleotide comprising a payload gene, a silencer effector cassette, and one or more silencer effector binding sequences.

Abstract: A marching memory includes an alternating periodic array of odd-numbered columns (U1, U2, . . . , Un?1, Un) and even-numbered columns (Ur1, Ur2, . . . , Urn?1, Urn). Each of the odd-numbered columns (U1, U2, . . . , Un?1, Un) has a sequence of front-stage cells aligned along a column direction so as to store a set of moving information of byte size or word size. And each of the even-numbered columns (Ur1, Ur2, . . . , Urn?1, Urn) has a sequence of rear-stage cells aligned along a column direction so as to store the set of moving information, so that the set of moving information can be transferred synchronously, step by step, along a direction orthogonal to the column direction.

Abstract: A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

Abstract: A marching memory includes an alternating periodic array of odd-numbered columns (U1, U2, . . . , Un?1, Un) and even-numbered columns (Ur1, Ur2, . . . , Urn?1, Urn). Each of the odd-numbered columns (U1, U2, . . . , Un?1, Un) has a sequence of front-stage cells aligned along a column direction so as to store a set of moving information of byte size or word size. And each of the even-numbered columns (Ur1, Ur2, . . . , Urn?1, Urn) has a sequence of rear-stage cells aligned along a column direction so as to store the set of moving information, so that the set of moving information can be transferred synchronously, step by step, along a direction orthogonal to the column direction.

Abstract: A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

Abstract: Methods and devices for connecting a mobile device with different data storage devices located either locally or remotely are provided. The device may apply one or more rules to create a hierarchical virtualization of the several data storage devices. The virtualization may then be provided to the user as a single, hierarchical file system. Further, a monitoring system may monitor the file system to determine if any new applications have been installed or if applications are currently being executed. If a connection is made to a secure network, the system may provide the information derived from the monitoring to the secure network. The secure network can then analyze the information to determine if any of the applications should be uninstalled from the device or should be stopped while the device is connected to the network.

Abstract: A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information of byte size or word size, the information of byte size or word size is transferred synchronously, step by step, along a direction orthogonal to a direction of the sequence of bit-level cells, each of the bit-level cells encompassing an electron-storage region configured to accumulate cell-electrons. The cell-electrons accumulated in an electron-storage region in a subject memory unit is directly transferred to an adjacent electron-storage region, which is assigned in the next memory unit adjacent to the subject memory unit, the transfer of the cell-electrons is directly controlled by control signals, without using a combinational function of a logic gate circuit.

Abstract: A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.

Abstract: A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information of byte size or word size, the information of byte size or word size is transferred synchronously, step by step, along a direction orthogonal to a direction of the sequence of bit-level cells, each of the bit-level cells encompassing an electron-storage region configured to accumulate cell-electrons. The cell-electrons accumulated in an electron-storage region in a subject memory unit is directly transferred to an adjacent electron-storage region, which is assigned in the next memory unit adjacent to the subject memory unit, the transfer of the cell-electrons is directly controlled by control signals, without using a combinational function of a logic gate circuit.

Abstract: Methods and devices for connecting a mobile device with different data storage devices located either locally or remotely are provided. The device may apply one or more rules to create a hierarchical virtualization of the several data storage devices. The virtualization may then be provided to the user as a single, hierarchical file system. Further, a monitoring system may monitor the file system to determine if any new applications have been installed or if applications are currently being executed. If a connection is made to a secure network, the system may provide the information derived from the monitoring to the secure network. The secure network can then analyze the information to determine if any of the applications should be uninstalled from the device or should be stopped while the device is connected to the network.