Abstract: A helmet for protecting an athlete from concussion or laceration during sporting activities is disclosed. The helmet is constructed of an outer shell and an inner cushion. The outer shell and inner cushion each have curvature relief cutouts to allow the helmet to be compressed to securely fit on the athlete's head. In addition, the outer shell and the inner cushion each have a front section and a rear section, the rear section defining an open section that allows the athlete a range of motion without interference by the helmet.

Abstract: A method and apparatus for fault tolerant communication among a plurality of I/O controllers and a communication controller using an I/O bus having byte-parallel and bit-serial data lines. Each controller is connected to the bit-serial and byte-parallel data lines and the CPU communication controller is capable of selectively indicating which set of lines shall be used for communicating information. When serial communication is desired, a switching signal is transmitted by the CPU communication controller on the serial data line whereupon the I/O controllers switch communication from the byte-parallel data lines to the bit-serial data line. Serial arbitration conflicts are avoided by allocating a time interval to each I/O controller. Each time interval is divided into 3-bit periods. An arbitrating I/O controller asserts the first itself bit true, asserts the second bit false, and disconnects from the bus during the third bit period to separate in time the modules connected to the bus from each other.

Abstract: A method and apparatus for recovery from a fault occurring within a computing system using a hardware recovery module comprising a microprocessor dedicated for recovery control and a memory for storing system states. A recovery counter counts machine instructions executed since a previously recorded initial checkpoint. Each time the CPU transfers information directly from an I/O controller or the cache memory the recovery module stores the data being transferred. Each time an interrupt is made to the CPU, the recovery module is notified of the interrupt, and it thereupon stores the count of machine instructions executed since the previously recorded initial checkpoint and information identifying the interrupt. When a fault is detected, the system is restored to the system state existing at the beginning of the checkpoint, and the processor synthetically executes the machine instructions originally executed after the initial checkpoint in a sequence substantially similar to the original sequence.

Abstract: A method and apparatus are presented which enable recovery from a fault occurrence within a computing system which occurs during an original execution of machine instructions. The computing system is reset to a previously recorded system state, and a re-execution of machine instructions is initiated. To repeat an asynchronous event at a point in the re-execution of machine instructions identical to a point at which the repeating event was handled in the original execution of machine instructions, machine instructions executed and re-executed are counted. During the re-execution of machine instructions, the computing system performs operations upon identical inputs, at identical points, that the computing system did during the original execution of machine instructions. The computing system is thereby restored to a final system state identical to a specified system state existing before fault occurrence.

Abstract: The invention is an improvement in the construction of the sailboard portion of windsurfers wherein the usual hard-foam slab hull typical of surfboard construction is replaced by a slab of soft foam, the only rigid structure of the entire board being a pair of closely spaced fiberglass stringers longitudinally extended along the midline of the board, and mounts for the mast, daggerboard and fin, which mounts are sandwiched between the two longitudinal stringers which are embedded centrally in the soft foam slab.