Abstract: A system, method, and computer program product are provided for assigning elements of a matrix to processing threads. In use, a matrix is received to be processed by a parallel processing architecture. Such parallel processing architecture includes a plurality of processors each capable of processing a plurality of threads. Elements of the matrix are assigned to each of the threads for processing, utilizing an algorithm that increases a contiguousness of the elements being processed by each thread.

Abstract: A system, method, and computer program product are provided for categorizing a plurality of vertices of a graph into independent sets. A random number is assigned to each vertex in the graph and the assigned number of each vertex is compared to the assigned numbers each of the neighbors of the vertex, where all vertices in the graph that have an assigned number greater than the assigned numbers of each of their neighbors are added to a first independent set, and all vertices in the graph that have an assigned number less than the assigned numbers of each of their neighbors are added to a second independent set separate from the first independent set.

Abstract: A system, method, and computer program product are provided for grouping linearly ordered primitives. In operation, a plurality of primitives are linearly ordered. Additionally, the primitives are grouped. Furthermore, at least one intersection query is performed, utilizing the grouping.

Abstract: A system, method, and computer program product are provided for performing a scan operation on a sequence of single-bit values using a parallel processing architecture. In operation, a scan operation instruction is received. Additionally, in response to the scan operation instruction, a scan operation is performed on a sequence of single-bit values using a parallel processor architecture with a plurality of processing elements.

Abstract: A system, method, and computer program product are provided for performing graph coloring. In use, a graph with a plurality of vertices is identified. Additionally, the plurality of vertices of the graph is categorized, where the categorizing of the plurality of vertices is optimized.

Abstract: A system, method, and computer program product are provided for assigning elements of a matrix to processing threads. In use, a matrix is received to be processed by a parallel processing architecture. Such parallel processing architecture includes a plurality of processors each capable of processing a plurality of threads. Elements of the matrix are assigned to each of the threads for processing, utilizing an algorithm that increases a contiguousness of the elements being processed by each thread.

Abstract: A system, method, and computer program product are provided for converting a reduction algorithm to a segmented reduction algorithm. In operation, a reduction algorithm is identified. Additionally, the reduction algorithm is converted to a segmented reduction algorithm. Furthermore, the segmented reduction algorithm is performed to produce an output.

Abstract: A ray tracing system, method, and computer program product are provided for simultaneously traversing a hierarchy of rays and a hierarchy of objects. In operation, a hierarchy of rays and a hierarchy of objects are simultaneously traversed. Additionally, ray tracing is performed, based on the traversal.

Abstract: A system, method, and computer program product are provided for organizing a plurality of rays. In operation, a plurality of rays is identified. Additionally, the rays are organized, utilizing a bounding volume.

Abstract: A system, method, and computer program product are provided for converting a scan algorithm to a segmented scan algorithm in an operator independent manner. In operation, a scan algorithm and a limit index data structure are identified. Utilizing the limit index data structure, the scan algorithm is converted to a segmented scan algorithm in an operator-independent manner. Additionally, the segmented scan algorithm is performed to produce an output.

Abstract: A system, method, and computer program product are provided for generating a ray tracing data structure utilizing a parallel processor architecture. In operation, a global set of data is received. Additionally, a data structure is generated utilizing a parallel processor architecture including a plurality of processors. Such data structure is adapted for use in performing ray tracing utilizing the parallel processor architecture, and is generated by allocating the global set of data among the processors such that results of processing of at least one of the processors is processed by another one of the processors.

Abstract: A system, method, and computer program product are provided for testing a query against multiple sets of objects. In operation, a query is tested against a first set of objects, utilizing a single instruction multiple data processing architecture. Additionally, a second set of objects is selected based on a result of testing the query against the first set of objects. Furthermore, the query is tested against the second set of objects, utilizing the single instruction multiple data processing architecture.

Abstract: A system, method, and computer program product are provided for performing a scan operation on a sequence of single-bit values using a parallel processing architecture. In operation, a scan operation instruction is received. Additionally, in response to the scan operation instruction, a scan operation is performed on a sequence of single-bit values using a parallel processor architecture with a plurality of processing elements.

Abstract: A system, method, and computer program product are provided for generating a ray tracing data structure utilizing a parallel processor architecture. In operation, a global set of data is received. Additionally, a data structure is generated utilizing a parallel processor architecture including a plurality of processors. Such data structure is adapted for use in performing ray tracing utilizing the parallel processor architecture, and is generated by allocating the global set of data among the processors such that results of processing of at least one of the processors is processed by another one of the processors.

Abstract: An apparatus for testing the racks and installation wiring of telephone switch equipment takes the form of a module capable of insertion into the various slots of a particular rack configuration. The module includes a circuit board which terminates in a connector suitable for interconnection with a particular telephone switch system, and which receives a continuity testing subassembly useful in performing the desired testing. To this end, selected contacts (or pins) of the connector are coupled with a light emitting diode (LED) and a biasing circuit for operating the LED responsive to connection of the biasing circuit to ground. Each LED, and the biasing circuit, is provided with a suitable operating voltage which can either be derived from the rack which is being tested or a battery which is resident in the test apparatus.