Abstract: A cross-connect for interfacing high-speed ports and having add/drop multiplexing capabilities for permitting simultaneous access to all individual subscribers may be improved by utilizing a switch block arrangement for allowing downstream subscribers to be switched among each other without the need to be switched upstream through the cross-connect or may alternatively be improved by substituting an expansion shelf in place of a line shelf so as to permit the addition of additional line shelves and hence, additional subscribers. This latter improvement is made possible by assuming that not all subscribers will need access to the cross-connect at the same time. A switch block for such arrangements can output either an input data signal previously stored in a switch memory or a daisy-chain input that is output from another switch block in the arrangement.

Abstract: During ISDN signal transmission from a network trunk line (21) to an access line (18), a word (202) provided from the network trunk line is broken into two bytes including a data byte (205) and a performance monitoring byte (206). After signal transmission through common equipment (14) and an access line shelf (10), a line card (12) verifies the composite parity of the data byte and the performance monitoring byte to determine if an ISDN signal transmission error has occurred. During ISDN signal transmission from an access line (18) to a network trunk line (21), the line card (12) forms a data byte (305) by combining pairs of data bits from the access line, and simultaneously forms a performance monitoring byte (306) by combining pairs of performance monitoring bits corresponding to the pairs of data bits.

Abstract: A line unit, used in a line shelf having a line shelf processor and common logic, is provided with an EEPROM device for storing information relative to the line unit. The stored information includes line unit type identification codes, auto provisioning data, gain and equalization adjustment data and signaling translation tables. The data contained within the EEPROM may be utilized by the line shelf processor to provide automatic initialization and provisioning of the line unit when first inserted into the line shelf, and automatic signaling translation so that line unit signaling becomes compatible with a transmission facility connected to the line shelf. The need for factory preset resistors installed in the line unit may be eliminated by storing within the EEPROM a required gain setting.

Abstract: A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Abstract: In a TDM telecommunications terminal, wherein multiple line cards are connected to a TDM bus, each line card location is provided with an identification code. A processor controlled circuit generates a programmable sequence of identification codes which are transmitted on a configuration bus in time slots synchronized with the time slots of the TDM bus. The configuration bus is connected to each of the line cards, which include a comparator logic circuit for comparing the identification of the line card location to the identification codes provided on the configuration bus. When a match is detected, the line card is enabled and is given access to the TDM bus. Through the programmable reassignment of time slots to line cards, concentration may be provided by the system, and a plurality of time slots may be assigned to a single line card to provide broad band service.

Abstract: A three-ported apparatus is adapted to interface a serial TDM bus, a local controller and a line unit bus in a telecommunications terminal. All data passing between the TDM bus and the line unit bus is temporarily stored and is accessible to the local controller, allowing the controller to either pass said data without modification or provide modifications thereto. Signaling contained within the data may be translated to a form usable by the line unit through the use of translation tables down-loaded from inventory storage on the line units. For each line unit, the local controller programmably controls time slot assignment, provisioning and inventory information access.

Abstract: A serial transport frame format is described which transfers data between two locations. The serial transport frame format comprises a fixed number of channels per frame, each channel having a predetermined size. One channel per frame contains frame synchronization information and each channel which conveys data, contains a first portion for the transfer of data and a second portion which contains associated control information.

Abstract: A variable length shift register is formed of a plurality of flip-flops arranged to form separate shift registers of different lengths. The shift registers are interconnected by multiplexers which connect either the input or the output of each shift register to the input of an adjacent shift register. Control signals are provided to the multiplexers to controllably select the length of the variable shift register by selectively inserting shift registers into the variable shift register and bypassing others.

Abstract: A line unit interface circuit used on line units in a line shelf of a digital loop carrier provides all of the logic necessary to access two subscriber lines to a line unit interface bus connected to common equipment within the line shelf. Information received from the common equipment includes signaling data, configuration data and provisioning data, which is reconfigured and processed by the line unit interface circuit for controlling the subscriber line channels. Configuration data from the common equipment is decoded to assign time slots on the line unit interface bus to the various channels serviced by the line shelf and to further provide for a timing offset between the transmit and receive strobes provided to each subscriber line circuit. A flywheel circuit is used to prevent erroneous time slot assignment in the event of noise or interference on the line unit interface bus.

Abstract: A p.c.m. encoder comprises a high accuracy linear A/D converter followed by a digital high pass filter, a d.c. offset circuit and a digital compressor. The high pass filter removes any d.c. offset from the encoded signal and the offset circuit then reintroduces a controlled amount of d.c. offset. By this means the performance can be improved especially in regard to idle noise and crosstalk enhancement.

Abstract: The digital multiplier is of the add and shift type with a matrix type input in which a number of serial data words can be applied simultaneously to the multiplier enabling the multiplier to compute simultaneously the sum of a number of products. This multiplier is intended for use in digital filters and single channel coders.