Patents by Inventor Michael J. Greger

Michael J. Greger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9991993
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for time offset validation of components with independent silicon clocks. A requesting component includes transmission logic to transmit timing protocol requests to a responding component, receiving logic to receive timing protocol responses, replay detection logic to detect a retransmission of a timing protocol message and to set an internal timing state of the requesting component as invalid, and validation logic to detect at least two consecutive timing protocol dialogs and set the internal timing state of the requesting component as valid. A responding component includes receiving logic, transmission logic, replay detection logic to detect a retransmission of a timing protocol message and set an internal timing state of the responding component as invalid, and validation logic to detect at least two consecutive timing protocol dialogs and set the internal timing state of the responding component as valid.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Anthony S. Bock, Michael J. Greger
  • Publication number: 20170288818
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for time offset validation of components with independent silicon clocks. A requesting component includes transmission logic to transmit timing protocol requests to a responding component, receiving logic to receive timing protocol responses, replay detection logic to detect a retransmission of a timing protocol message and to set an internal timing state of the requesting component as invalid, and validation logic to detect at least two consecutive timing protocol dialogs and set the internal timing state of the requesting component as valid. A responding component includes receiving logic, transmission logic, replay detection logic to detect a retransmission of a timing protocol message and set an internal timing state of the responding component as invalid, and validation logic to detect at least two consecutive timing protocol dialogs and set the internal timing state of the responding component as valid.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Anthony S. BOCK, Michael J. Greger
  • Patent number: 6553439
    Abstract: A local integrated circuit device provides remote configuration access to one or more remote integrated circuit devices. The local integrated circuit device receives configuration access requests through at least two interfaces. The local integrated circuit device accesses a configuration space of one or more remote integrated circuit devices in accordance with the received configuration access requests.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: April 22, 2003
    Assignee: Intel Corporation
    Inventors: Michael J. Greger, Eric R. Wehage, Toshiyuki Sakuta