Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.

Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.

Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.

Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.

Abstract: A digital process monitor for measuring the performance of an integrated circuit has been developed. The digital process monitor includes: a ring oscillator that generates a series of clocked pulses, and a ripple counter that counts the clocked pulses. The count is measured for a prescribed period of time and the count corresponds to the performance of the integrated circuit.

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract: A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with a pair of more lightly doped base portions that encroach substantially into the intrinsic base below the main intrinsic base portion. The two deep encroaching base portions extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced. Manufacture of the transistor entails introducing suitable dopants into a semiconductor body. In one fabrication process, a fast-diffusing dopant is employed in forming the deep encroaching base portions without significantly affecting earlier-created transistor regions.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract: A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with a pair of more lightly doped base portions that encroach substantially into the intrinsic base below the main intrinsic base portion. The two deep encroaching base portions extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: A masking method for use in a silicide formation process is disclosed herein which prevents an oxide etching solution from tunneling under a photoresist masking layer and damaging oxide spacers not intended to be etched. This process may be used during the formation of a bipolar or MOS transistor formed in an isolated silicon island. A mask opening used to etch exposed oxide spacer portions is made to not expose any parasitic oxide spacers formed along an edge of the isolated silicon island. In this way, an oxide etch solution is prevented from tunneling along the parasitic oxide spacer and reaching any intersecting oxide spacers not intended to be etched. The desired oxide spacers will thus be intact to properly isolate silicide portions formed over exposed silicon and polysilicon surfaces.

Abstract: In a bipolar transistor, the collector and the base are formed in an isolation region laterally bounded by a field insulator. The isolation region corners are spaced far from the emitter to reduce the collector-emitter leakage current. The base does not extend laterally throughout the isolation region. Thus the base is small and the collector-base capacitance is small as a result. Those corners of the isolation region that are not covered by a base contact region are covered and contacted by an insulator. This insulator prevents the field insulator from being pulled back during wafer clean steps. Consequently, the field insulator does not expose the collector. Further, the insulator covering the corners prevents the metal silicide on the surface of the extrinsic base from contacting the corners. The insulator overlying the corners thus reduces the collector-base leakage current.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.