Abstract: In one embodiment, a processor comprises one or more registers coupled to an execution core. The registers are configured to store an intercept configuration that identifies which of a plurality of intercept events are enabled for intercept during guest execution. Additionally, the intercept configuration identifies, for each enabled intercept event, which of at least two exit mechanisms are to be used in response to detection of the enabled intercept event. The execution core is configured to detect one of the enabled intercept events during execution of a guest and to exit the guest using the exit mechanism identified in the intercept configuration for that detected, enabled intercept event.

Abstract: In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space.

Abstract: In one embodiment, a processor comprises an execution core, a level 1 (L1) data cache coupled to the execution core and configured to store data, and a transient/transactional cache (TTC) coupled to the execution core. The execution core is configured to generate memory read and write operations responsive to instruction execution, and to generate transactional read and write operations responsive to executing transactional instructions. The L1 data cache is configured to cache memory data accessed responsive to memory read and write operations to identify potentially transient data and to prevent the identified transient data from being stored in the L1 data cache. The TTC is also configured to cache transaction data accessed responsive to transactional read and write operations to track transactions. Each entry in the TTC is usable for transaction data and for transient data.

Abstract: In one embodiment, a processor comprises an execution core, a level 1 (L1) data cache coupled to the execution core and configured to store data, and a transient/transactional cache (TTC) coupled to the execution core. The execution core is configured to generate memory read and write operations responsive to instruction execution, and to generate transactional read and write operations responsive to executing transactional instructions. The L1 data cache is configured to cache memory data accessed responsive to memory read and write operations to identify potentially transient data and to prevent the identified transient data from being stored in the L1 data cache. The TTC is also configured to cache transaction data accessed responsive to transactional read and write operations to track transactions. Each entry in the TTC is usable for transaction data and for transient data.

Abstract: In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space.

Abstract: In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space.

Abstract: A mechanism for performing locked operations in a processing unit. A dispatch unit may dispatch a plurality of instructions including a locked instruction and a plurality of non-locked instructions. One or more of the non-locked instructions may be dispatched before and after the locked instruction. An execution unit may execute the plurality of instructions including the non-locked and locked instruction. A retirement unit may retire the locked instruction after execution of the locked instruction. During retirement, the processing unit may begin enforcing a previously obtained exclusive ownership of a cache line accessed by the locked instruction. Furthermore, the processing unit may stall the retirement of the one or more non-locked instructions dispatched after the locked instruction until after the writeback operation for the locked instruction is completed.

Abstract: In an embodiment, a computer system comprises a processor; a memory management module comprising a plurality of instructions executable on the processor; a memory coupled to the processor; and an input/output memory management unit (IOMMU) coupled to the memory. The IOMMU is configured to implement address translation and memory protection for memory operations sourced by one or more input/output (I/O) devices. The memory stores a command queue during use. The memory management module is configured to write one or more control commands to the command queue, and the IOMMU is configured to read the control commands from the command queue and execute the control commands.

Abstract: In an embodiment, an input/output memory management unit (IOMMU) is configured to receive a completion wait command defined to ensure that one or more preceding invalidation commands are completed by the IOMMU prior to a completion of the completion wait command. The IOMMU is configured to respond to the completion wait command by delaying completion of the completion wait command until: (1) a read response corresponding to each outstanding memory read operation that depends on a translation entry that is invalidated by the preceding invalidation commands is received; and (2) the control unit transmits one or more operations upstream to ensure that each memory write operation that depends on the translation table entry that is invalidated by the preceding invalidation commands has at least reached a bridge to a coherent fabric in the computer system and has become visible to the system.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a cache to cache translation data from memory; and a control unit coupled to the cache. The control unit is configured to implement address translation and memory protection for memory requests sourced by one or more input/output (I/O) devices. The memory requests sourced by the I/O devices travel in one or more first virtual channels, and the control unit is configured to transmit memory requests sourced by the control unit in at least a second virtual channel separate from the first virtual channels.

Abstract: A flexible architecture is presented that allows either Synchronous Optical Network (SONET) framing, Optical Transport Network (OTN) framing, or SONET framing followed by OTN framing. The architecture consists of SONET frame processors, OTN frame processors, and a configurable selection network.

Abstract: In one embodiment, a processor comprises one or more registers coupled to an execution core. The registers are configured to store an intercept configuration that identifies which of a plurality of intercept events are enabled for intercept during guest execution. Additionally, the intercept configuration identifies, for each enabled intercept event, which of at least two exit mechanisms are to be used in response to detection of the enabled intercept event. The execution core is configured to detect one of the enabled intercept events during execution of a guest and to exit the guest using the exit mechanism identified in the intercept configuration for that detected, enabled intercept event.

Abstract: A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.

Abstract: A flexible architecture is presented that allows either Synchronous Optical Network (SONET) framing, Optical Transport Network (OTN) framing, or SONET framing followed by OTN framing. The architecture consists of SONET frame processors, OTN frame processors, and a configurable selection network.

Abstract: A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.