Patents by Inventor Michael J. Hajeck
Michael J. Hajeck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9251381Abstract: A solid-state storage subsystem, such as a non-volatile memory card or drive, includes a main memory area that is accessible via standard memory access commands (such as ATA commands), and a restricted memory area that is accessible only via one or more non-standard commands. The restricted memory area stores information used to control access to, and/or use of, information stored in the main memory area. As one example, the restricted area may store one or more identifiers, such as a unique subsystem identifier, needed to decrypt an executable or data file stored in the main memory area. A host software component is configured to retrieve the information from the subsystem's restricted memory area, and to use the information to control access to and/or use of the information in the main memory area.Type: GrantFiled: December 29, 2011Date of Patent: February 2, 2016Assignee: Western Digital Technologies, Inc.Inventors: David E. Merry, Mark Diggs, Gary A. Drossel, Michael J. Hajeck
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Patent number: 8127048Abstract: A storage subsystem comprises a set of zone definitions that uses physical block addresses to divide a memory array in the storage subsystem into zones or segments. A set of zone parameters defines user access modes and security levels for each of the segments. Defining zones for the memory array provide flexibility and increased protection for data stored in the memory array. For example, data of one zone can be quickly erased without affecting data stored in other zones and critical data can be stored in read-only zones to prevent inadvertent overwrite.Type: GrantFiled: March 18, 2011Date of Patent: February 28, 2012Assignee: SiliconSystems, Inc.Inventors: David E. Merry, Mark S. Diggs, Gary A. Drossel, Michael J. Hajeck
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Patent number: 8108692Abstract: A solid-state storage subsystem, such as a non-volatile memory card or drive, includes a main memory area that is accessible via standard memory access commands (such as ATA commands), and a restricted memory area that is accessible only via one or more non-standard commands. The restricted memory area stores information used to control access to, and/or use of, information stored in the main memory area. As one example, the restricted area may store one or more identifiers, such as a unique subsystem identifier, needed to decrypt an executable or data file stored in the main memory area. A host software component is configured to retrieve the information from the subsystem's restricted memory area, and to use the information to control access to and/or use of the information in the main memory area.Type: GrantFiled: June 27, 2006Date of Patent: January 31, 2012Assignee: SiliconSystems, Inc.Inventors: David E. Merry, Mark Diggs, Gary A. Drossel, Michael J. Hajeck
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Patent number: 7936603Abstract: A storage system that comprises multiple solid-state storage devices includes a command set that enables a host system to initiate one or more types of purge operations. The supported purge operations may include an erase operation in which the storage devices are erased, a sanitization operation in which a pattern is written to the storage devices, and/or a destroy operation in which the storage devices are physically damaged via application of a high voltage. The command set preferably enables the host system to specify how many of the storage devices are to be purged at a time during a purge operation. The host system can thereby control the amount of time, and the current level, needed to complete the purge operation. In some embodiments, the number of storage devices that are purged at a time may additionally or alternatively be selectable by a controller of the storage system.Type: GrantFiled: September 29, 2008Date of Patent: May 3, 2011Assignee: SiliconSystems, Inc.Inventors: David E. Merry, Jr., Michael J. Hajeck
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Patent number: 7912991Abstract: A storage subsystem comprises a set of zone definitions that uses physical block addresses to divide a memory array in the storage subsystem into zones or segments. A set of zone parameters defines user access modes and security levels for each of the segments. Defining zones for the memory array provide flexibility and increased protection for data stored in the memory array. For example, data of one zone can be quickly erased without affecting data stored in other zones and critical data can be stored in read-only zones to prevent inadvertent overwrite.Type: GrantFiled: March 23, 2009Date of Patent: March 22, 2011Assignee: Siliconsystems, Inc.Inventors: David E. Merry, Mark S. Diggs, Gary A. Drossel, Michael J. Hajeck
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Patent number: 7898855Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it loses its power connection to the host system.Type: GrantFiled: March 6, 2009Date of Patent: March 1, 2011Assignee: Siliconsystems, Inc.Inventors: David E. Merry, Jr., Michael J. Hajeck
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Patent number: 7765373Abstract: A solid-state storage subsystem, such as a non-volatile memory card or drive, includes a main memory area that is accessible via standard memory access commands (such as ATA commands), and a restricted memory area that is accessible only via one or more non-standard commands. The restricted memory area stores information used to control access to, and/or use of, information stored in the main memory area. As one example, the restricted area may store one or more identifiers, such as a unique subsystem identifier, needed to decrypt an executable or data file stored in the main memory area. A host software component is configured to retrieve the information from the subsystem's restricted memory area, and to use the information to control access to and/or use of the information in the main memory area.Type: GrantFiled: June 27, 2006Date of Patent: July 27, 2010Assignee: Siliconsystems, Inc.Inventors: David E. Merry, Mark Diggs, Gary A. Drossel, Michael J. Hajeck
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Publication number: 20090196100Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it looses its power connection to the host system.Type: ApplicationFiled: March 6, 2009Publication date: August 6, 2009Applicant: SILICONSYSTEMS, INC.Inventors: David E. Merry, JR., Michael J. Hajeck
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Patent number: 7509441Abstract: A storage subsystem comprises a set of zone definitions that uses physical block addresses to divide a memory array in the storage subsystem into zones or segments. A set of zone parameters defines user access modes and security levels for each of the segments. Defining zones for the memory array provide flexibility and increased protection for data stored in the memory array. For example, data of one zone can be quickly erased without affecting data stored in other zones and critical data can be stored in read-only zones to prevent inadvertent overwrite.Type: GrantFiled: June 30, 2006Date of Patent: March 24, 2009Assignee: SiliconSystems, Inc.Inventors: David E. Merry, Mark S. Diggs, Gary A. Drossel, Michael J. Hajeck
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Patent number: 7502256Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it looses its power connection to the host system.Type: GrantFiled: November 30, 2004Date of Patent: March 10, 2009Assignee: Siliconsystems, Inc.Inventors: David E. Merry, Jr., Michael J. Hajeck
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Publication number: 20090031095Abstract: A storage system that comprises multiple solid-state storage devices includes a command set that enables a host system to initiate one or more types of purge operations. The supported purge operations may include an erase operation in which the storage devices are erased, a sanitization operation in which a pattern is written to the storage devices, and/or a destroy operation in which the storage devices are physically damaged via application of a high voltage. The command set preferably enables the host system to specify how many of the storage devices are to be purged at a time during a purge operation. The host system can thereby control the amount of time, and the current level, needed to complete the purge operation. In some embodiments, the number of storage devices that are purged at a time may additionally or alternatively be selectable by a controller of the storage system.Type: ApplicationFiled: September 29, 2008Publication date: January 29, 2009Applicant: SiliconSystems, Inc.Inventors: David E. Merry, JR., Michael J. Hajeck
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Patent number: 7447807Abstract: A storage subsystem comprises a set of zone definitions that uses physical block addresses to divide a memory array in the storage subsystem into zones or segments. A set of zone parameters defines user access modes and security levels for each of the segments. Defining zones for the memory array provide flexibility and increased protection for data stored in the memory array. For example, data of one zone can be quickly erased without affecting data stored in other zones and critical data can be stored in read-only zones to prevent inadvertent overwrite.Type: GrantFiled: June 30, 2006Date of Patent: November 4, 2008Assignee: Siliconsystems, Inc.Inventors: David E. Merry, Mark S. Diggs, Gary A. Drossel, Michael J. Hajeck
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Patent number: 7430136Abstract: A storage system that comprises multiple solid-state storage devices includes a command set that enables a host system to initiate one or more types of purge operations. The supported purge operations may include an erase operation in which the storage devices are erased, a sanitization operation in which a pattern is written to the storage devices, and/or a destroy operation in which the storage devices are physically damaged via application of a high voltage. The command set preferably enables the host system to specify how many of the storage devices are to be purged at a time during a purge operation. The host system can thereby control the amount of time, and the current level, needed to complete the purge operation. In some embodiments, the number of storage devices that are purged at a time may additionally or alternatively be selectable by a controller of the storage system.Type: GrantFiled: July 18, 2006Date of Patent: September 30, 2008Assignee: Siliconsystems, Inc.Inventors: David E. Merry, Jr., Michael J. Hajeck
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Patent number: 7126857Abstract: A storage subsystem, such as a flash memory card, includes a voltage detection circuit that monitors the power signal from a host system to detect anomalies. The voltage detection circuit responds to a power signal anomaly by asserting a signal, such as a busy signal on a standard ready/busy signal line, to block the host system from performing write operations to the storage subsystem during presence of the anomaly. The storage system may also include a backup power source, such as a charge pump circuit, a capacitive array, and/or a rechargeable battery, that provides power to a controller of the storage subsystem during the presence of the anomaly, such that the storage system can complete outstanding operations.Type: GrantFiled: January 18, 2005Date of Patent: October 24, 2006Assignee: SiliconSystems, Inc.Inventor: Michael J. Hajeck
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Patent number: 6856556Abstract: A storage subsystem, such as a flash memory card, includes a charge pump that receives a power signal from a host system, and generates a regulated power signal that is provided to the storage subsystem's controller. When the power signal from the host is interrupted, the charge pump additionally acts as a backup power supply such that the storage subsystem can continue to operate temporarily. The storage subsystem also includes a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein. The voltage detection circuit responds to detection of an anomaly by asserting a busy signal to block the host system from performing write operations to the storage subsystem. By asserting the busy signal, the voltage detection circuit substantially ensures that the backup, regulated power provided by the charge pump will be sufficient for the controller to complete all outstanding operations.Type: GrantFiled: April 3, 2003Date of Patent: February 15, 2005Assignee: Siliconsystems, Inc.Inventor: Michael J. Hajeck