Abstract: A power system is disclosed that includes a chassis configured to house one or more boards in which the boards are electrically coupled to one another. The boards are configured to receive external power and to output power using a plurality of different voltages. The boards are configured to receive power from at least one internal power source electrically coupled boards and to output power using a plurality of different voltages. The boards include one or more converters configured to convert power. The one or more converters are thermally interfaced with one or more portions of the chassis.

Abstract: A power system is disclosed that includes a chassis configured to house one or more boards in which the boards are electrically coupled to one another. The boards are configured to receive external power and to output power using a plurality of different voltages. The boards are configured to receive power from at least one internal power source electrically coupled boards and to output power using a plurality of different voltages. The boards include one or more converters configured to convert power. The one or more converters are thermally interfaced with one or more portions of the chassis.

Abstract: A power system is disclosed that includes a chassis configured to house a first board, a second board, and a third board, in which the boards are electrically coupled to one another. The first board is configured to receive power and to output power at a first voltage and a second voltage. The second board is configured to receive power from the first board or at least one internal battery electrically coupled to the second board and to output power using at least two voltages. The third board is configured to receive power from the second board and to output power at two voltages. The boards include one or more converters configured to convert power. The one or more converters are thermally interfaced with one or more portions of the chassis so as to conduct heat into a respective portion of the chassis.

Abstract: A power system is disclosed that includes a chassis configured to house a first board, a second board, and a third board, in which the boards are electrically coupled to one another. The first board is configured to receive power and to output power at a first voltage and a second voltage. The second board is configured to receive power from the first board or at least one internal battery electrically coupled to the second board and to output power using at least two voltages. The third board is configured to receive power from the second board and to output power at two voltages. The boards include one or more converters configured to convert power. The one or more converters are thermally interfaced with one or more portions of the chassis so as to conduct heat into a respective portion of the chassis.

Abstract: An indium phosphate semiconductor substrate is prepared for subsequent growth of epitaxial layers to form a semiconductor device. In the preparation, the substrate is first annealed to promote any tendency for surface accumulation of impurity atoms by diffusion from the substrate and to promote impurity atom removal from the surface of the substrate. The substrate is then surface etched to remove further impurities and to provide a clean, flat surface for subsequent epitaxial layer growth. The final stage of preparation involves growing a semi-insulating buffer layer on the substrate to isolate the device epitaxial layers from the substrate.

Abstract: It has been found that layers which include arsenic and/or zinc can have an adverse effect upon optoelectronic semiconductor devices such as lasers. This is reduced by treatments in which arsenic and zinc are excluded. Preferably the substrate is cooled from reaction temperature in the presence of a mixture of hydrogen and PH.sub.3 (replacing AsH.sub.3 and/or Zn(CH.sub.3).sub.2 used to grow the final layer). Alternatively, devices have a contact layer of heavily p-type gallium indium arsenide are improved by the deposition of a protective layer of indium phosphide. This layer is removed immediately before metalization. Even though the protective layer is not present in the final product it has a beneficial effect.