Patents by Inventor Michael J. Hartig

Michael J. Hartig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11764257
    Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: September 19, 2023
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
  • Publication number: 20220130953
    Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
  • Patent number: 11271076
    Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 8, 2022
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
  • Patent number: 11245003
    Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 8, 2022
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
  • Publication number: 20200203477
    Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.
    Type: Application
    Filed: July 19, 2019
    Publication date: June 25, 2020
    Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
  • Publication number: 20200203476
    Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.
    Type: Application
    Filed: July 19, 2019
    Publication date: June 25, 2020
    Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
  • Patent number: 8802565
    Abstract: Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Hartig, Sivananda K. Kanakasabapathy, Soon-Cheon Seo, Raghavasimhan Sreenivasan
  • Publication number: 20140070414
    Abstract: Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael J. Hartig, Sivananda K. Kanakasabapathy, Soon-Cheon Seo, Raghavasimhan Sreenivasan
  • Patent number: 6245686
    Abstract: A process for forming a semiconductor device includes placing a substrate (104) into an apparatus (300), creating a plasma, and processing the substrate (104). The apparatus (300) includes an electromagnetic source (120), a bulk material (302), and a first barrier layer (304). The bulk material (302) is between the electromagnetic source (120) and an interior (126) of the apparatus (300). The first barrier layer (304) is between the bulk material (302) and the interior (126). A process for operating an apparatus (300) includes forming a polymer layer along an inorganic layer (302, 306or 702), wherein the polymer layer is formed within the apparatus (300); removing the polymer layer to expose the inorganic layer (302, 306, or 702); and etching at least a portion of the exposed inorganic layer (302, 306, or 702). Typically, the inorganic layer (203, 306, or 702) is semiconductive or resistive.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: June 12, 2001
    Assignee: Motorola Inc.
    Inventors: Jeffrey D. Rose, Michael J. Hartig, David G. Farber, Danny R. Babbitt, Jason A. Rivers, Ai Koh, Terry G. Sparks
  • Patent number: 6165567
    Abstract: A film is formed over a substrate using a physical vapor deposition method. When using ionized metal plasma physical vapor deposition, the deposition chamber configuration or operating parameters are adjusted to achieve the desired film characteristics. If the film is to be substantially uniform in thickness across a substrate, the deposition species density is made higher at locations away from the center of the substrate.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: December 26, 2000
    Assignee: Motorola, Inc.
    Inventors: Peter Lowell George Ventzek, Daniel G. Coronell, Michael J. Hartig, John C. Arnold
  • Patent number: 5683548
    Abstract: An inductively coupled plasma reactor and method for processing a semiconductor wafer (28). The inductively coupled plasma reactor (10) includes a plasma source (16) having a plurality of channels (38, 44) in which processing gases are independently supplied to each channel. A gas supply system (20) includes a plurality of gas feed lines (34, 35, 36) each capable of supplying an individual flow rate and gas composition to the plurality of channels (38, 44) in the plasma source (16). Each channel is surrounded by an independently powered RF coil (54, 56), such that the plasma density can be varied within each channel (38, 44) of the plasma source (16). In operation, a material layer (66) overlying a semiconductor wafer (28) is either uniformly etched or deposited by localized spatial control of the plasma characteristics at each location (64) across the semiconductor wafer (28).
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: November 4, 1997
    Assignee: Motorola, Inc.
    Inventors: Michael J. Hartig, John C. Arnold