Abstract: A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e.g., multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU.

Abstract: An apparatus for simulating error conditions associated with an integrated circuit, the integrated circuit being an in-line component of an electronic circuit. The apparatus, in response to the receipt of specified commands, accepts and stores data and control information, the control information including an integrated circuit pin specification portion and a voltage level specification portion, the data information specifying integrated circuit pin number identification. Two decoders decode the voltage level specification and integrated circuit pin specification portions of the stored control information, respectively. A switching circuit connected to a source of voltage levels and to the electronic circuit, and responsive to the decoded integrated circuit pin specification, applies to the integrated circuit pin specified by the stored data information a voltage level specified by the decoded voltage level specification.