Patents by Inventor Michael J. Heideman

Michael J. Heideman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9594707
    Abstract: Systems and methods for performing data input/output (I/O) operations using a computer network communications link are described. A method may include assigning a block of virtual addresses for usage with at least one computer network communications link. The method may also include registering the entire block of virtual addresses prior to an operating system partition performing I/O operations using the at least one computer network communications link, wherein registering comprises setting a plurality of virtual page frame numbers of the block of virtual addresses to point to distinct pages of physical memory. In some embodiments, one or more I/O operations may be performed using the at least one computer network communications link and the registered block of virtual addresses.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 14, 2017
    Assignee: Unisys Corporation
    Inventors: Michael J Heideman, E. Brian Garrett, Steven M Wierdsma, Carl R Crandall
  • Publication number: 20160062912
    Abstract: Systems and methods for performing data input/output (I/O) operations using a computer network communications link are described. A method may include assigning a block of virtual addresses for usage with at least one computer network communications link. The method may also include registering the entire block of virtual addresses prior to an operating system partition performing I/O operations using the at least one computer network communications link, wherein registering comprises setting a plurality of virtual page frame numbers of the block of virtual addresses to point to distinct pages of physical memory. In some embodiments, one or more I/O operations may be performed using the at least one computer network communications link and the registered block of virtual addresses.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 3, 2016
    Applicant: UNISYS CORPORATION
    Inventors: MICHAEL J. HEIDEMAN, E. BRIAN GARRETT, STEVEN M. WIERDSMA, CARL R. CRANDALL
  • Patent number: 7873868
    Abstract: An apparatus for and method of enhancing reliability and performance within a cluster lock processing system having a relatively large number of commodity instruction processors which are managed by a highly scalable, off the shelf platform. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the cluster/lock processors assume the responsibility for providing these functions. The low cost of the commodity instruction processors makes the system almost linearly scalable. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform which performs the role of the cluster/lock master. The validity operation throughput of the clustered systems manager is increased by aging out validity entries for each of the process owners via a background operation. This minimizes the number of exclusive locks that must be utilized while performing a validity operation.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: January 18, 2011
    Assignee: Unisys Corporation
    Inventors: Michael J. Heideman, Dennis R. Konrad, David A. Novak
  • Publication number: 20080155224
    Abstract: A legacy operating system (OS) of a type generally associated with an enterprise-level, legacy data processing platform such as a mainframe is instead provided on a commodity data processing platform such as a personal computer. The legacy OS is adapted to communicate with legacy IOP devices of the type generally associated with the legacy platform to provide data protection mechanisms for legacy data. To initiate an I/O operation, a commodity OS executing on the commodity platform allocates a memory buffer and provides the virtual buffer address to the legacy OS. The legacy OS uses this address to construct a description of an I/O operation to be performed using the buffer. The description is then translated from one referencing a first memory page size in virtual address space into a description referencing a different page size in physical address space so that legacy IOP can complete the operation.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Inventors: Carl R. Crandall, Michael J. Heideman, Michael C. Otto, John T. Rusterholz
  • Patent number: 7366765
    Abstract: An apparatus for and method of implementing a cluster lock processing system using highly scalable, off-the-shelf commodity processors. The cluster lock processing system is the central component of a clustered computer system, providing locking and coordination between multiple host systems. The host systems are coupled to the cluster lock processing system using off-the-shelf, low latency interconnects. The cluster lock processing system is composed of multiple commodity platforms that are also coupled to each other using low latency interconnects. Failure of one of the commodity platforms that comprise the cluster lock processing system results in no loss of functionality or interruption of service. This is made possible through the use of specialized software that runs on the commodity platforms. Through the use of custom software and inexpensive hardware the overall system cost is dramatically reduced when compared to typical solutions that use custom built hardware.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: April 29, 2008
    Assignee: Unisys Corporation
    Inventors: Michael J. Heideman, Dennis R. Konrad, David A. Novak
  • Patent number: 7246255
    Abstract: An apparatus for and method of enhancing reliability within a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are managed by a cluster lock manager. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the cluster/lock processors assume the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform which performs the role of the cluster/lock master. Upon failure of this hardware platform, a second redundant hardware platform converts from slave to master role. The logic for the failure detection and role swapping is placed within software, which can run as an application under a commonly available operating system.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: July 17, 2007
    Assignee: Unisys Corporation
    Inventors: Michael J. Heideman, Dennis R. Konrad, David A. Novak
  • Patent number: 7181642
    Abstract: An apparatus for and method of enhancing throughput within a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are arranged in redundant fashion to improve reliability. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the cluster/lock processors assume the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform which performs the role of the cluster/lock master. Upon failure of this hardware platform, a second redundant hardware platform converts from slave to master role. The logic for the failure detection and role swapping is placed within software, which can run as an application under a commonly available operating system.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: February 20, 2007
    Assignee: Unisys Corporation
    Inventors: Michael J. Heideman, Dennis R. Konrad, David A. Novak
  • Patent number: 7178057
    Abstract: An apparatus for and method of providing failure recovery from redundancy, notwithstanding that the failed subsystem and its replacement have differing capacities. This is especially useful when implementing a cluster lock processing system having a relatively large number of commodity instruction processors which are managed by a highly scalable, cluster lock manager. Reliability is built into the managing communication processor by dividing the system into master and slave subsystems. The master has primary responsibility for system management and coordination, whereas the slave has primary responsibility to backup the master and be prepared to assume management responsibility. Upon the need to transfer responsibility from the master to the slave, whether it be manual (e.g., maintenance) or automatic (e.g., failure), the only concern is that the slave has sufficient capacity to accept the current level of processing, even though it does not have the same level of capacity as the master.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: February 13, 2007
    Assignee: Unisys Corporation
    Inventors: Michael J. Heideman, Dennis R. Konrad, David A. Novak
  • Patent number: 7155638
    Abstract: An apparatus for and method of enhancing reliability within a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are managed by a cluster lock manager. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the cluster/lock processors assume the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform which performs the role of the master. Upon failure of this hardware platform, a second redundant hardware platform converts from slave to master role. The logic for the failure detection and role swapping is placed within software, which can run as an application under a commonly available operating system.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: December 26, 2006
    Assignee: Unisys Corporation
    Inventors: Michael J. Heideman, Dennis R. Konrad, David A. Novak, Carl R. Crandall
  • Patent number: 7149923
    Abstract: An apparatus for and method of enhancing reliability within a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are managed by a cluster lock manager. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the communication processor assumes the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform which performs the role of the cluster/lock master. Upon failure of this hardware platform, a second redundant hardware platform converts from slave to master role. The logic for the failure detection and role swapping is placed within software, which can run as an application under a commonly available operating system.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: December 12, 2006
    Assignee: Unisys Corporation
    Inventors: Michael J. Heideman, Dennis R. Konrad, David A. Novak
  • Patent number: 7043580
    Abstract: An apparatus for and method of implementing a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are managed by a highly scalable, off the shelf communication processor. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the communication processor assumes the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. Furthermore, having a fully scalable communication processor ensures a completely scalable system. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform. The architecture may be implemented using any of a wide variety of proprietary or non-proprietary operating system environments.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: May 9, 2006
    Assignee: Unisys Corporation
    Inventors: Michael J. Heideman, Thomas P. Cooper, Ronald Q. Smith
  • Patent number: 7000046
    Abstract: An apparatus for and method of implementing a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are managed by a highly scalable, off the shelf communication processor. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the communication processor assumes the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. Furthermore, having a fully scalable communication processor ensures a completely scalable system. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: February 14, 2006
    Assignee: Unisys Corporation
    Inventors: Thomas P. Cooper, Carl R. Crandall, Thomas N. DeVries, Michael J. Heideman, Craig B. Johnson, David A. Novak, Michael C. Otto, Haeng D. Park
  • Patent number: 6789133
    Abstract: A system and method for processing I/O requests in a computing system. I/O packets are created via an operating system associated with the computing system, where the I/O packets include I/O transaction information. The I/O packets are made accessible to an I/O system. A command for a channel type connecting a target I/O component to the I/O system is constructed, where this command construction is based on the I/O transaction information provided in the I/O packet, and based on physical aspects of the target I/O component and channel type provided independently of the I/O packet. The constructed command is issued to the target I/O component in accordance with the channel type.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: September 7, 2004
    Assignee: Unisys Corporation
    Inventors: Carl R. Crandall, Thomas N. DeVries, Craig B. Johnson, Joseph E. Kessler, Michael C. Otto, Haeng D. Park, Michael J. Heideman
  • Patent number: 5949970
    Abstract: A data processing system including a first and second host, a first and second outboard file cache connected to the first host, and a first and second secondary storage device connected to the first host. The system operation includes the first host reading file data from the first or second secondary storage device after the data is cached on both the first and second outboard file caches. File data is updated by writing to both first and second outboard file caches. File data is destaged by writing data from the first outboard file cache only, to first and second secondary storage devices. Failure of a single outboard file cache is handled by the first host not reading and writing to the failed outboard file cache. Site-wide failure of first host, first outboard file cache, and first secondary storage device is handled by establishing communication from second host to both second outboard file cache and second secondary storage device and resuming processing.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: September 7, 1999
    Assignee: Unisys Corporation
    Inventors: Ralph E. Sipple, Thomas P. Cooper, Dennis R. Konrad, Michael J. Heideman
  • Patent number: 5940826
    Abstract: A computer system having dual outboard devices for generating audit trail sequence numbers and performing file locking. One embodiment includes a master and a slave outboard device, where lock request handling includes a lock request first sent to the master, lock grant awaited, followed by a request sent to the slave. Unlock request handling includes sending an unlock request to slave first, followed by sending an unlock request to the master. Obtaining a system sequence number includes always reading the slave outboard device, then reading the master outboard device. The computer system includes a method for switching host processors from a single outboard device mode to a dual outboard device mode and back again in the event of failure of one of the outboard devices.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: August 17, 1999
    Assignee: Unisys Corporation
    Inventors: Michael J. Heideman, Thomas P. Cooper