Patents by Inventor Michael J. Jackson
Michael J. Jackson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220344494Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.Type: ApplicationFiled: June 24, 2022Publication date: October 27, 2022Inventors: Subhash JOSHI, Michael J. JACKSON, Michael L. HATTENDORF
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Patent number: 11411095Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.Type: GrantFiled: December 29, 2017Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Subhash Joshi, Michael J. Jackson, Michael L. Hattendorf
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Publication number: 20190165172Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.Type: ApplicationFiled: December 29, 2017Publication date: May 30, 2019Inventors: Subhash JOSHI, Michael J. JACKSON, Michael L. HATTENDORF
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Publication number: 20180344335Abstract: A patient matched instrument for a patient's femur is disclosed. The instrument includes a body having a cutting slot and a patient matched surface that mates with the patient's trochlear groove, a first leg portion extending from the body, a second leg portion extending from the body; and each leg portion has a contacting pad for tangential contact with the patient's femoral medial and lateral condyles.Type: ApplicationFiled: August 10, 2018Publication date: December 6, 2018Inventors: Brian W. MCKINNON, Eric S. KENNEDY, Michael J. JACKSON, Randy C. WINEBARGER, Zachary C. WILKINSON
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Patent number: 10070876Abstract: A patient matched instrument for a patient's femur is disclosed. The instrument includes a body having a cutting slot and a patient matched surface that mates with the patient's trochlear groove, a first leg portion extending from the body, a second leg portion extending from the body; and each leg portion has a contacting pad for tangential contact with the patient's femoral medial and lateral condyles.Type: GrantFiled: July 15, 2013Date of Patent: September 11, 2018Assignee: Smith & Nephew, Inc.Inventors: Brian W. McKinnon, Eric S. Kennedy, Michael J. Jackson, Randy C. Winebarger, Zachary C. Wilkinson
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Patent number: 9966440Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstrained channel structures.Type: GrantFiled: October 17, 2014Date of Patent: May 8, 2018Assignee: INTEL CORPORATIONInventors: Glenn A. Glass, Anand S. Murthy, Michael J. Jackson, Harold W. Kennel
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Publication number: 20170229342Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, ANAND S. MURTHY, MICHAEL J. JACKSON, MICHAEL L. HATTENDORF, SUBHASH M. JOSHI
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Patent number: 9633835Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).Type: GrantFiled: September 6, 2013Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Glenn A. Glass, Anand S. Murthy, Michael J. Jackson, Michael L. Hattendorf, Subhash M. Joshi
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Publication number: 20150201952Abstract: A patient matched instrument for a patient's femur is disclosed. The instrument includes a body having a cutting slot and a patient matched surface that mates with the patient's trochlear groove, a first leg portion extending from the body, a second leg portion extending from the body; and each leg portion has a contacting pad for tangential contact with the patient's femoral medial and lateral condyles.Type: ApplicationFiled: July 15, 2013Publication date: July 23, 2015Applicant: Smith & Nephew, Inc.Inventors: Brian W. McKinnon, Eric S. Kennedy, Michael J. Jackson, Randy C. Winbarger, Zachary C. Wilkinson
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Publication number: 20150069473Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Inventors: Glenn A. Glass, Anand S. Murthy, Michael J. Jackson, Michael L. Hattendorf, Subhash M. Joshi
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Publication number: 20150054031Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstrained channel structures.Type: ApplicationFiled: October 17, 2014Publication date: February 26, 2015Applicant: Intel CorporationInventors: GLENN A. GLASS, ANAND S. MURTHY, MICHAEL J. JACKSON, HAROLD W. KENNEL
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Patent number: 8896066Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures.Type: GrantFiled: November 26, 2012Date of Patent: November 25, 2014Assignee: Intel CorporationInventors: Glenn A. Glass, Anand S. Murthy, Michael J. Jackson, Harold W. Kennel
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Publication number: 20140018813Abstract: A patient matched instrument for a patient's femur is disclosed. The instrument includes a body having a cutting slot and a patient matched surface that mates with the patient's trochlear groove, a first leg portion extending from the body, a second leg portion extending from the body; and each leg portion has a contacting pad for tangential contact with the patient's femoral medial and lateral condyles.Type: ApplicationFiled: July 15, 2013Publication date: January 16, 2014Applicant: Smith & Nephew, Inc.Inventors: Brian W. MCKINNON, Eric S. KENNEDY, Michael J. JACKSON, Randy C. WINEBARGER, Zachary C. WILKINSON
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Patent number: 8495946Abstract: A camouflage material comprising an electromagnetic energy (EME) absorbing layer comprising an array of carbon nanotubes and a plurality of energy transmitting elements embedded within the absorbing material. The energy transmitting elements are operative to convey energy to at least a portion of an outer surface of the absorbing layer.Type: GrantFiled: June 16, 2011Date of Patent: July 30, 2013Assignee: Lockheed Martin CorporationInventors: Michael J. Jackson, Daniel Spooner
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Publication number: 20130154016Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures.Type: ApplicationFiled: November 26, 2012Publication date: June 20, 2013Inventors: Glenn A. Glass, Anand S. Murthy, Michael J. Jackson, Harold W. Kennel
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Publication number: 20120318129Abstract: A camouflage material comprising an electromagnetic energy (EME) absorbing layer comprising an array of carbon nanotubes and a plurality of energy transmitting element embedded within the absorbing material. The energy transmitting elements are operative to convey energy to at least a portion of an outer surface of the absorbing layer.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Applicant: Lockheed Martin CorporationInventors: Michael J. Jackson, Daniel Spooner
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Patent number: 7823331Abstract: A seal assembly is provided for a side-by-side or French style door on a refrigerator in which the sealing gasket is supported on a gasket carrier and pivotably coupled to a base member adapted to be secured along the medial vertical edge of a refrigerator door. A set of magnets are supported by the gasket carrier opposite the gasket. These magnets are arranged such that similar poles are adjacent one another when the doors are in the closed position. The magnets provide a repelling force which operates to rotate the gaskets into sealing engagement with one another.Type: GrantFiled: November 16, 2006Date of Patent: November 2, 2010Assignee: Holm Industries, Inc.Inventors: Gregory R. Linkmeyer, Michael J. Jackson
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Publication number: 20090175131Abstract: Described is an alarm clock for playing selected audio files according to a time-based schedule. More specifically, the alarm clock is adapted to maintain a calendar and a clock and to store a plurality of audio files. The alarm clock assigns each audio file a corresponding date and time, and when an assigned date and time occurs, the alarm clock plays the corresponding audio file such that file is perceivable by a user.Type: ApplicationFiled: January 9, 2009Publication date: July 9, 2009Inventor: Michael J. Jackson
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Patent number: 5255452Abstract: A system for allowing a shoe wearer to lean forwardly beyond his center of gravity by virtue of wearing a specially designed pair of shoes which will engage with a hitch member movably projectable through a stage surface. The shoes have a specially designed heel slot which can be detachably engaged with the hitch member by simply sliding the shoe wearer's foot forward, thereby engaging with the hitch member.Type: GrantFiled: June 29, 1992Date of Patent: October 26, 1993Assignee: Triumph International, Inc.Inventors: Michael J. Jackson, Michael L. Bush, Dennis Tompkins