Patents by Inventor Michael J. Jarcy

Michael J. Jarcy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7298711
    Abstract: According to one exemplary embodiment, a communication device comprises a line driver, where the line driver provides an output signal. The communication device further comprises a digital echo canceller module coupled to the line driver, where the digital echo canceller module receives an echo reference signal determined by the output signal of the line driver, where the echo canceller module outputs an echo cancellation signal, and where the echo cancellation signal is capable of canceling linear and non-linear components of a composite signal. The communication device further comprises a summation module coupled to the digital echo canceller module, where the summation module receives the echo cancellation signal and the composite signal, and where the composite signal comprises a received signal and the linear and non-linear echo components. The summation module is configured to subtract the echo cancellation signal from the composite signal and to output the received signal.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: November 20, 2007
    Assignee: Mindspeed Technologies, Inc.
    Inventor: Michael J. Jarcy
  • Patent number: 6787895
    Abstract: According to one embodiment, a semiconductor die is situated in a cutout section of a substrate. In one embodiment, the substrate is situated on a printed circuit board such that the semiconductor die situated in the cutout section of the substrate is also situated on a support pad on the top surface of the printed circuit board. In one embodiment, a semiconductor die bond pad on the semiconductor die is connected to a substrate bond pad on the substrate. In one embodiment, an interconnect trace on the substrate is connected to an interconnect pad on the top surface of the printed circuit board.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: September 7, 2004
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael J. Jarcy, Andrew R. Gizara, Evans S. McCarthy, Robbie U. Villanueva, Hassan S. Hashemi, Mahyar S. Dadkhah
  • Patent number: 6104230
    Abstract: An electronic inductor circuit comprises a pair of cascoded Darlington bipolar or MOSFET transistors, configured such that the impedance presented by the collector (drain) of the top transistor of the electronic inductor is increased, relative to the other resistive components in the electronic inductor circuit and DAA. The impedance is increased to a magnitude such that small fluctuations in the collector (drain) impedance do not vary the over-all electronic inductor circuit impedance. Therefore, as heat generated by the circuit causes the impedance of the transistor in the electronic inductor to change, the impedance change does not adversely affect over-all modem circuit performance.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: August 15, 2000
    Assignee: Conexant Systems, Inc.
    Inventor: Michael J. Jarcy