Patents by Inventor Michael J. Kasper

Michael J. Kasper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030094347
    Abstract: A sortation system and method includes providing a sorter assembly and a slug-building assembly. Product is received by the sorter assembly and sorted to a series of sortation lanes. The slug-building assembly includes a plurality of supply lines supplying product for sorting by the sorter assembly. At least one of the supply lines includes an accumulation conveyor and a slug conveyor. Product is accumulated in slug portions at the accumulation conveyor. Slug portions are combined into product slugs at the slug conveyor. Product slugs are discharged from the slug conveyor for sorting by the sorter assembly.
    Type: Application
    Filed: November 19, 2002
    Publication date: May 22, 2003
    Inventors: Ted W. Haan, Clinton R. Lupton, Michael J. Kasper, Jerry J. Bukoski
  • Patent number: 6229811
    Abstract: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: May 8, 2001
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, M. Magdy Talaat, Yun-Che Wang, Michael J. Kasper
  • Patent number: 6055241
    Abstract: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: April 25, 2000
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, M. Magdy Talaat, Yun-Che Wang, Michael J. Kasper