Abstract: A level shifter includes first and second input terminals, first and second output terminals, first pull-down circuitry operable to pull down one of the first and second output terminals responsive to signals present on the first and second input terminals, first pull-up circuitry operable to pull up the first output terminal responsive to a signal present on the second output terminal or pull up the second output terminal responsive to a signal present on the first output terminal, and second pull-up circuitry operable to pull up one of the first and second output terminals responsive to the signals present on the first and second input terminals.

Abstract: A level shifter includes first and second input terminals, first and second output terminals, first pull-down circuitry operable to pull down one of the first and second output terminals responsive to signals present on the first and second input terminals, first pull-up circuitry operable to pull up the first output terminal responsive to a signal present on the second output terminal or pull up the second output terminal responsive to a signal present on the first output terminal, and second pull-up circuitry operable to pull up one of the first and second output terminals responsive to the signals present on the first and second input terminals.

Abstract: A process compensation circuit for an inverting element of a CMOS device, including a duplicate inverting element connected in parallel with the inverting element of the CMOS device. An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the output of the inverting element of the CMOS device. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.

Abstract: An output of a common mode differential amplifier is initialized to a known state, which includes inputting a voltage to a network conductor of an electronic assembly, where the network conductor is coupled to a first input node of a first differential input of the amplifier. The amplifier is on an integrated circuit chip of the assembly and has a self-bias node. Circuitry of the amplifier normally adjusts to obtain an equilibrium voltage on the self-bias node in response to the inputted voltages. To initialize the amplifier output, however, preset circuitry on the integrated circuit chip overrides the normal equilibrium voltage on the self-bias node, forcing the self-bias node to a predetermined voltage regardless of the amplifier input voltages. In response, the amplifier produces an desired initial output state on a first output node of the amplifier.

Abstract: A level shifter circuit is disclosed. The level shifter circuit includes a first level shifter circuit and a second level shifter circuit. The first level shifter circuit and the second level shifter circuit are substantially identical with each other. The second level shifter circuit coupled to the first level shifter circuit via a couple of transistor to provide an output and a complementary output, respectively.

Abstract: A level shifter circuit is disclosed. The level shifter circuit includes a first level shifter circuit and a second level shifter circuit. The first level shifter circuit and the second level shifter circuit are substantially identical with each other. The second level shifter circuit is coupled to the first level shifter circuit via a couple of transistors to provide an output and a complementary output, respectively.