Patents by Inventor Michael J. Manfra

Michael J. Manfra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030030078
    Abstract: An MOS transistor comprising a substrate, a source, a drain, and a gate, wherein the gate comprises aluminum nitride. Aluminum nitride is epitaxially grown on the silicon substrate at a substrate temperature of about 600° C. and subsequently annealed at a substrate temperature of about 950° C.
    Type: Application
    Filed: October 7, 2002
    Publication date: February 13, 2003
    Inventors: Michael J. Manfra, Loren N. Pfeiffer, Kenneth W. West, Yiu-Huen Wong
  • Patent number: 6495409
    Abstract: An MOS transistor comprising a substrate, a source, a drain, and a gate, wherein the gate comprises aluminum nitride. Aluminum nitride is epitaxially grown on the silicon substrate at a substrate temperature of about 600° C. and subsequently annealed at a substrate temperature of about 950° C.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: December 17, 2002
    Assignee: Agere Systems Inc.
    Inventors: Michael J. Manfra, Loren N. Pfeiffer, Kenneth W. West, Yiu-Huen Wong
  • Patent number: 5411914
    Abstract: A new III-V buffer or passivation material is described which is produced by low temperature growth (LTG) of III-V compounds. The material has unique and desirable properties, particularly for closely spaced, submicron gate length active III-V semiconductor FET devices, such as HEMT's, MESFET's and MISFET's. The LTG material is grown under ambient conditions which incorporate an excess of the more volatile of the III-V species into the grown material. The new material is crystalline, highly resistive, relatively insensitive to light, and can be overgrown with high quality III-V active layers or used as a passivation material to insulate and protect active device structures.
    Type: Grant
    Filed: May 15, 1992
    Date of Patent: May 2, 1995
    Assignee: Massachusetts Institute of Technology
    Inventors: Chang-Lee Chen, Leonard J. Mahoney, Michael J. Manfra, Frank W. Smith, Arthur R. Calawa
  • Patent number: 4952527
    Abstract: A new III-IV buffer material is described which is produced by low temperature growth of III-V compounds by MBE that has unique and desirable properties, particularly for closely spaced, submicron gate length active III-V semiconductor devices, such as HEMT's, MESFET's and MISFET's. In the case of the III-V material, GaAs, the buffer is grown under arsenic stable growth conditions, at a growth rate of 1 micron/hour, and at a substrate temperature preferably in the range of 150 to about 300.degree. C. The new material is crystalline, highly resistive, optically inactive, and can be overgrown with high quality III-V active layers.
    Type: Grant
    Filed: February 19, 1988
    Date of Patent: August 28, 1990
    Assignee: Massachusetts Institute of Technology
    Inventors: Arthur R. Calawa, Frank W. Smith, Michael J. Manfra, Chang-Lee Chen
  • Patent number: 4323422
    Abstract: A method and apparatus for polishing surfaces so as to provide surfaces which are optically flat and damage free. An etch solution is applied to a rotating surface and the surface to be prepared is caused by hydroplane on the etch solution, the hydroplaning action producing the desired optically flat surface.
    Type: Grant
    Filed: April 24, 1980
    Date of Patent: April 6, 1982
    Inventors: Arthur R. Calawa, Joseph V. Gormley, Michael J. Manfra