Abstract: A solid-state photodetector with variable spectral response that can produce a narrow or wide response spectrum of incident light. Some embodiments include a solid-state device structure that includes a first photodiode and a second photodiode that share a common anode region. Bias voltages applied to the first photodiode and/or the second photodiode may be used to control the thicknesses of depletion regions of the photodiodes and/or a common anode region to vary the spectral response of the photodetector. Thickness of the depletion regions and/or the common anode region may be controlled based on resistance between multiple contacts of the common anode region and/or capacitance of the depletion regions. Embodiments include control circuits and methods for determining spectral characteristics of incident light using the variable spectral response photodetector.

Abstract: A solid-state photodetector with variable spectral response that can produce a narrow or wide response spectrum of incident light. Some embodiments include a solid-state device structure that includes a first photodiode and a second photodiode that share a common anode region. Bias voltages applied to the first photodiode and/or the second photodiode may be used to control the thicknesses of depletion regions of the photodiodes and/or a common anode region to vary the spectral response of the photodetector. Thickness of the depletion regions and/or the common anode region may be controlled based on resistance between multiple contacts of the common anode region and/or capacitance of the depletion regions. Embodiments include control circuits and methods for determining spectral characteristics of incident light using the variable spectral response photodetector.

Abstract: A solid-state photodetector with variable spectral response that can produce a narrow or wide response spectrum of incident light. Some embodiments include a solid-state device structure that includes a first photodiode and a second photodiode that share a common anode region. Bias voltages applied to the first photodiode and/or the second photodiode may be used to control the thicknesses of depletion regions of the photodiodes and/or a common anode region to vary the spectral response of the photodetector. Thickness of the depletion regions and/or the common anode region may be controlled based on resistance between multiple contacts of the common anode region and/or capacitance of the depletion regions. Embodiments include control circuits and methods for determining spectral characteristics of incident light using the variable spectral response photodetector.

Abstract: A solid-state photodetector with variable spectral response that can produce a narrow or wide response spectrum of incident light. Some embodiments include a solid-state device structure that includes a first photodiode and a second photodiode that share a common anode region. Bias voltages applied to the first photodiode and/or the second photodiode may be used to control the thicknesses of depletion regions of the photodiodes and/or a common anode region to vary the spectral response of the photodetector. Thickness of the depletion regions and/or the common anode region may be controlled based on resistance between multiple contacts of the common anode region and/or capacitance of the depletion regions. Embodiments include control circuits and methods for determining spectral characteristics of incident light using the variable spectral response photodetector.

Abstract: A method for measuring a capacitance of a device under test is provided that includes selectively charging and discharging a first conductor with a first set of p and n element-pairs in response to a voltage potential applied to the first set of p and n element-pairs. The method further includes selectively charging and discharging a second conductor with a second set of p and n element-pairs in response to a voltage potential applied to the second set of p and n element-pairs. Currents are measured at drains associated with the first set of p element-pairs as the first and second conductors charge and discharge such that a capacitance associated with the first conductor may be determined that is based on the drain currents.

Abstract: A method for measuring a capacitance of a semiconductor is provided that includes positioning a measurement circuit in a scribe line area associated with the semiconductor. The scribe line area is indicative of a delineation that separates one or more portions of the semiconductor. A capacitance of one or more elements included within the one or more portions of the semiconductor is then measured using the measurement circuit. The method also includes comparing the capacitance measurement of the one or more elements included within the one or more portions of the semiconductor to a reference set of capacitance values such that a parameter associated with a manufacturing process that generated the semiconductor may be checked.

Abstract: A method for measuring a capacitance of a semiconductor is provided that includes positioning a measurement circuit in a scribe line area associated with the semiconductor. The scribe line area is indicative of a delineation that separates one or more portions of the semiconductor. A capacitance of one or more elements included within the one or more portions of the semiconductor is then measured using the measurement circuit. The method also includes comparing the capacitance measurement of the one or more elements included within the one or more portions of the semiconductor to a reference set of capacitance values such that a parameter associated with a manufacturing process that generated the semiconductor may be checked.

Abstract: A method for measuring a capacitance of a device under test is provided that includes selectively charging and discharging a first conductor with a first set of p and n element-pairs in response to a voltage potential applied to the first set of p and n element-pairs. The method further includes selectively charging and discharging a second conductor with a second set of p and n element-pairs in response to a voltage potential applied to the second set of p and n element-pairs. Currents are measured at drains associated with the first set of p element-pairs as the first and second conductors charge and discharge such that a capacitance associated with the first conductor may be determined that is based on the drain currents.

Abstract: Methods and apparatus for implementing charge skimming and variable integration time in focal plane arrays formed in a silicon substrate. The present invention provides for pulsing a field plate that lies over a diode disposed in the substrate in order to provide for charge skimming and variable integration time. The field plate is normally dc biased to suppress diode edge leakage. No additional structure is needed in the silicon substrate, and basic readout clocking is unaffected. Any interline transfer focal plane array can benefit from using the principles of the present invention.

Abstract: The fill factor in a Pt:Si imager is greatly improved by (1) biasing the reflector plate as a field plate to eliminate the need for an N.sup.- guard ring along the edges of the imaging diodes; (2) reconfiguring the meander channel to use a single meander channel for two columns of diodes; and (3) using a self-demultiplexing output bus structure which requires no separate array space for clocking buses. Two different types of dual-sided meander channel are described.

Abstract: A programmable voltage offset circuit (PVOC) (1) comprises a temporary latch memory (7); a latch disable circuit (5) which selects that PVOC (1) among several such circuits which may be simultaneously present on the same semiconductor chip; a resistor array (3); and a programmable nonvolatile memory (37). The desired voltage offsets V(OFFSET)s are temporarily produced in an iterative manner using the latch memory (7). Quasi-permanent voltage offsets V(OFFSET)s are then programmed using the nonvolatile memories (37), each of which typically comprises an EPROM (39). Application of an avalanche voltage V(STORE) to a PFET (43) portion of the EPROM (39) causes the PFET (43) to avalanche, thereby selectively programming the nonvolatile memory (37), depending upon the status of a signal supplied from the latch memory (7).

Abstract: A programmable voltage offset circuit (PVOC) (1) comprises a temporary latch memory (7); a latch disable circuit (5) which selects that PVOC (1) among several such circuits which may be simultaneously present on the same semiconductor chip; a resistor array (3); and a programmable nonvolatile memory (37). The desired voltage offsets V(OFFSET)s are temporarily produced in an iterative manner using the latch memory (7). Quasi-permanent voltage offsets V(OFFSET)s are then programmed using the nonvolatile memories (37), each of which typically comprises an EPROM (39). Application of an avalanche voltage V(STORE) to a PFET (43) portion of the EPROM (39) causes the PFET (43) to avalanche, thereby selectively programming the nonvolatile memory (37), depending upon the status of a signal supplied from the latch memory (7).

Abstract: A semiconductor integrated circuit using charged coupled device (CCD) technology for performing demodulation of time-varying signals which have been phase or amplitude modulated. The CCD circuit performs a sampling of the time-varying signal at a suitable sampling frequency depending upon the frequency of the phase or amplitude modulation of the carrier. The CCD device converts the sample into an equivalent charge packet which is used to control the control electrode of a field effect transistor in an amplifier circuit. The magnitude of the sample is representative of the amplitude of the carrier so that the output of the field effect transistor represents a demodulated signal. The circuit is a broad spectrum device, operable with a signal frequency from the audio into the gigaHertz (GHz) frequency range.

Abstract: A semiconductor integrated circuit using charged coupled device (CCD) technology for performing demodulation of time-varying signals which have been phase or amplitude modulated. The CCD circuit performs a sampling of the time-varying signal at a suitable sampling frequency depending upon the frequency of the phase or amplitude modulation of the carrier. The CCD device converts the sample into an equivalent charge packet which is used to control the control electrode of a field effect transistor in an amplifier circuit. The magnitude of the sample is representative of the amplitude of the carrier so that the output of the field effect transistor represents a demodulated signal. The circuit is a broad spectrum device, operable with a signal frequency from the audio into the gigaHertz (GHz) frequency range.

Abstract: A charge coupled digital-to-analog converter in which the digital input lines are connected to respective storage wells which store a predetermined amount of charge corresponding to the significance of the input line. A transfer gate is also provided for substantially simultaneously transferring and combining the charge packets to an analog output.

Abstract: A digital-to-analog optical recorder incorporating both CCD and integrated optics technologies which is fabricated as a single integral unit including an electro-optical layer portion and a semiconductor layer portion. Sampling circuits and digital-to-analog converters are implemented on the semiconductor layer portion using CCD technology, and a plurality of optical channel waveguides and electro-optical modulators are implemented on the electro-optical layer portion. Each digital signal is converted into two complementary light spots at the output of the recorder.