Abstract: An asymmetric digital subscriber loop modem may achieve efficiency and cost reduction by providing a coder/decoder (codec) chip which transmits data externally of the chip when the data is at a reduced or lower data rate. That is, instead of transmitting the data at a higher data rate, which may result in increased cost, for example for EMI shielding, the codec chip transmits the data when the data is at a reduced data rate.

Abstract: A bus repeater with voltage conversion and multiplexing circuits for use between devices with incompatible voltage levels communicating over inter-integrated circuit (I2C) buses. Bi-directional data and clock lines are passed through the circuit from one bus to the other, blocked so they are not passed on, or modified before being passed on, depending on the current transaction. The repeater is placed between two separate I2C buses and communicates between the two buses. To accommodate the slow-slave requirements of an I2C bus, the duration of signals on the clock line may be modified.

Abstract: A PCI bus system for a computer provides a main board with one or more PCI slots mounted on the board, and with each PCI slot adapted to receive a PHI card. Each PCI slot includes a plurality of electrical contacts. A multiplexor is provided for each PCI slot, and each multiplexor has at least first and second sets of electrical inputs selectively connectable to a set of outputs connected to a first set of the electrical contacts on its respective PCI slot. A link controller is provided for each PCI slot, with each link controller mounted on the main board. A first plurality of electrical lines for each PCI slot connect the respective link controller to the first set of electrical inputs on the respective multiplexor. A PCI controller is mounted on the main board, with a second plurality of electrical lines connecting the PHI controller to the second set of electrical inputs on the multiplexor.

Abstract: A bus repeater with voltage conversion and multiplexing circuits for use between devices with incompatible voltage levels communicating over inter-integrated circuit (I2C) buses. Bi-directional data and clock lines are passed through the circuit from one bus to the other, blocked so they are not passed on, or modified before being passed on, depending on the current transaction. The repeater is placed between two separate I2C buses and communicates between the two buses. To accommodate the slow-slave requirements of an I2C bus, the duration of signals on the clock line may be modified.

Abstract: A PCI bus system for a computer provides a main board with one or more PCI slots mounted on the board, and with each PCI slot adapted to receive a PCI card. Each PCI slot includes a plurality of electrical contacts. A multiplexor is provided for each PCI slot, and each multiplexor has at least first and second sets of electrical inputs selectively connectable to a set of outputs connected to a first set of the electrical contacts on its respective PCI slot. A link controller is provided for each PCI slot, with each link controller mounted on the main board. A first plurality of electrical lines for each PCI slot connect the respective link controller to the first set of electrical inputs on the respective multiplexor. A PCI controller is mounted on the main board, with a second plurality of electrical lines connecting the PCI controller to the second set of electrical inputs on the multiplexor.

Abstract: A bus repeater with voltage conversion and multiplexing circuits for use between devices with incompatible voltage levels communicating over inter-integrated circuit (I2C) buses. Bi-directional data and clock lines are passed through the circuit from one bus to the other, blocked so they are not passed on, or modified before being passed on, depending on the current transaction. The repeater is placed between two separate I2C buses and communicates between the two buses. Separating the two buses in this manner permits each bus to operate at a different voltage. Multiplexing is achieved by including logic in the repeater to recognize a first address associated with the repeater received from the first bus, and pass subsequent addresses and their associated messages through to the second bus to be decoded and processed by the devices on that bus. When the first address is not associated with the repeater, subsequent addresses and their associated messages are ignored and not passed through.

Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

Abstract: A PCI bus system for a computer provides a main board with one or more PCI slots mounted on the board, and with each PCI slot adapted to receive a PCI card. Each PCI slot includes a plurality of electrical contacts. A multiplexor is provided for each PCI slot, and each multiplexor has at least first and second sets of electrical inputs selectively connectable to a set of outputs connected to a first set of the electrical contacts on its respective PCI slot. A link controller is provided for each PCI slot, with each link controller mounted on the main board. A first plurality of electrical lines for each PCI slot connect the respective link controller to the first set of electrical inputs on the respective multiplexor. A PCI controller is mounted on the main board, with a second-plurality of electrical lines connecting the PCI controller to the second set of electrical inputs on the multiplexor.

Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

Abstract: A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.

Abstract: A method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge includes a bus activity monitor for monitoring bus cycles on a first bus, an inbound posting buffer, and a control logic. The control logic indicates whether to grant control of the first bus to a first processor on the first bus based on whether the inbound posting buffer is empty, and also controls disabling of posting to the inbound posting buffer. The control logic disables inbound posting responsive to both the first processor being backed off the system bus a predetermined number of times and the inbound posting buffer being empty.

Abstract: A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.

Abstract: A hybrid decoding module which resides on the computer system's high speed memory bus. The computer system incorporating the hybrid decoding module scheme is capable of having centrally decoded resources on the memory bus as well as resources capable of decoding memory bus addresses directly. During system initialization, or after a hard reset, the decoding logic polls each of the resources on the memory bus to determine whether the resource is a centrally decoded resource or a distributed decode resource. A table is maintained for all centrally decoded resources such that when addresses are put out by the processor during run-time, the decoding logic is capable of directing control to the centrally decoded resource. Another aspect of the present invention is implemented during the initialization of the system. When resources are polled by the decoding logic, they are also provided with an identifier which identifies the last available I/O space slot.

Abstract: A hybrid decoding module which resides on the computer system's high speed memory bus. The computer system incorporating the hybrid decoding module scheme is capable of having centrally decoded resources on the memory bus as well as resources capable of decoding memory bus addresses directly. During system initialization, or after a hard reset, the decoding logic polls each of the resources on the memory bus to determine whether the resource is a centrally decoded resource or a distributed decode resource. A table is maintained for all centrally decoded resources such that when addresses are put out by the processor during run-time, the decoding logic is capable of directing control to the centrally decoded resource. Another aspect of the present invention is implemented during the initialization of the system. When resources are polled by the decoding logic, they are also provided with an identifier which identifies the last available I/O space slot.