Abstract: In a general aspect, a quantum computing method is described. In some aspects, a control system in a quantum computing system assigns subsets of qubit devices in a quantum processor to respective cores. The control system identifies boundary qubit devices residing between the cores in the quantum processor and generates control sequences for each respective core. A signal delivery system in communication with the control system and the quantum processor receives control signals to execute the control sequences, and the control signals are applied to the respective cores in the quantum processor.

Abstract: The invention relates to transgenic animals useful for optimal production of functional immunoglobulins with human idiotypes.

Abstract: The invention relates to polynucleotides, particularly chimeric polynucleotides useful for optimal production of functional immunoglobulins with human idiotypes in rodents. The invention further relates to rodents comprising such polynucleotides.

Abstract: Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.

Abstract: The invention relates to polynucleotides, particularly chimeric polynucleotides useful for optimal production of functional immunoglobulins with human idiotypes in rodents. The invention further relates to rodents comprising such polynucleotides.

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: The invention relates to polynucleotides, particularly chimeric polynucleotides useful for optimal production of functional immunoglobulins with human idiotypes in rodents. The invention further relates to rodents comprising such polynucleotides.

Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.

Abstract: Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.

Abstract: A method of controlling voltage in a circuit is provided. Within the circuit, a block of an electrical component provides an indication that it desires to switch states (such as from off to on, on to off, or from one speed to another). The change in states requires a different current draw by the electrical component block. The indication is received by an electrical component that controls the voltage of the circuit. The electrical component that controls the voltage then issues a signal granting permission for the electrical component block to switch states. This permission signal is received by the electrical component and the electrical component block changes state.

Abstract: An informative packaging and wrapping product is described. The informative packaging and wrapping product includes a presentation surface and an informational surface coupled to the presentation surface that together form a packaging insert. The packaging insert is configured to reside within a shipping container. The packaging insert is configured to cover at least a portion of goods within the shipping container.

Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.

Abstract: Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions.

Abstract: Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.

Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.

Abstract: A method and device for setting a processor performance profile for a processor that is unable to directly measure voltage supplied by a voltage regulator includes determining a voltage requested of the voltage regulator and determining a first characteristic of a first portion of the electrical component. The first characteristic is one of power consumed by the first portion of the electrical component and load presented by the first portion of the electrical component. A first current is then determined by using the first voltage, the first characteristic, and a known relationship therebetween. A third voltage that is an estimate of the voltage supplied by the voltage regulator is then determined by comparing the first current to load line characteristics of the electrical component. The third voltage is then used to manage performance of the processor.

Abstract: The invention relates to polynucleotides, particularly chimeric polynucleotides useful for optimal production of functional immunoglobulins with human idiotypes in rodents. The invention further relates to rodents comprising such polynucleotides.

Abstract: A processor that dynamically remaps logical cores to physical cores is disclosed. In one embodiment, the processor includes a plurality of physical cores, and is configured to store a mapping of logical cores to the plurality of physical cores. The processor further includes an assignment unit configured to remap the logical cores to the plurality of physical cores subsequent to a boot process of the processor. In some embodiments, the assignment unit is configured to remap the logical cores in response to receiving an indication that one or more of the plurality of physical cores have entered an idle state. The processor may be configured to load a first of the plurality of physical cores with an execution state of a second of the plurality of physical cores upon the first physical core exiting an idle state.

Abstract: Described are a system and method for managing a data exchange in a network environment. A flowtag is assigned to a data packet at a source device. The flowtag includes a port identification corresponding to a port at an aggregation device. A destination device is in communication with the port at the aggregation device. The data packet is authenticated at the aggregation device. The data packet is output from the source device to the destination device via the aggregation device according to the port identification in the flowtag of the authenticated data packet.

Abstract: Described are systems and methods for interconnecting devices. A switch fabric is in communication with a plurality of electronic devices. A rendezvous memory is in communication with the switch fabric. Data is transferred to the rendezvous memory from a first electronic device of the plurality of electronic devices in response to a determination that the data is ready for output from a memory at the first electronic device and in response to a location allocated in the rendezvous memory for the data.