Abstract: A pressure relief valve having two rigid sealing surfaces lapped to a smoothness Ra of 8 micro-inches or less, and flatness within 80 micro-inches, forms a reliable seal by direct contact therebetween without an elastomer. The sealing surfaces and surrounding structures can be made of one or more metals, such as alloys of stainless steel, and can be CTE-matched, so that the valve is not impeded by environmental temperature changes. In a disclosed embodiment, a “poppet” is axially pressed against a seal plate by a spring. The poppet can be axially stabilized by sliding within a surrounding cylinder or spacer, and can contact the surrounding surface with a plurality of “arms” that reduce friction and enable gas flow therebetween. The poppet can be made from anti-galling Nitronic 60 alloy, and the surrounding structures can be stainless steel. Embodiments are suitable for low-pressure gas applications in extreme environments.

Abstract: A pressure relief valve having two rigid sealing surfaces lapped to a smoothness Ra of 8 micro-inches or less, and flatness within 80 micro-inches, forms a reliable seal by direct contact therebetween without an elastomer. The sealing surfaces and surrounding structures can be made of one or more metals, such as alloys of stainless steel, and can be CTE-matched, so that the valve is not impeded by environmental temperature changes. In a disclosed embodiment, a “poppet” is axially pressed against a seal plate by a spring. The poppet can be axially stabilized by sliding within a surrounding cylinder or spacer, and can contact the surrounding surface with a plurality of “arms” that reduce friction and enable gas flow therebetween. The poppet can be made from anti-galling Nitronic 60 alloy, and the surrounding structures can be stainless steel. Embodiments are suitable for low-pressure gas applications in extreme environments.

Abstract: A single-chip microcomputer device contains on-chip program storage in a read-only memory (ROM), and this program may be corrected or updated by patching. The ROM addresses are applied to an off-chip memory device containing one bit for each potential ROM address, and each bit is set to mark the beginning address of code to be patched; an interrupt is signalled when one of these set bits is accessed by an address occurring during operation of the microcomputer. The interrupt causes the processor to branch to an off-chip program memory to insert the patch code. The patch ends in a branch back to the on-chip ROM.