Patents by Inventor Michael J. Peter
Michael J. Peter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10676663Abstract: The present disclosure relates to formulations comprising an electrolyzed carrier fluid, optionally with an organic solvent and/or an additive. The formulations may be applied to in-situ and ex-situ hydrocarbon sources to recover or improve the hydrocarbon material.Type: GrantFiled: March 18, 2016Date of Patent: June 9, 2020Assignee: STRATEGIC RESOURCE OPTIMIZATION, INC.Inventors: John D. Breedlove, Michael J. Peters, Seth R. Mayer, David D. Faulder
-
Patent number: 9445602Abstract: A method for electrolytically generating a biocide, including providing a brine solution carrier fluid; providing a vessel for creating a first passageway and a second passageway, flowing the carrier fluid through the vessel; applying an electric potential to the electrodes to produce an anolyte fluid, an anolyte gas, a catholyte fluid, and a catholyte gas in the vessel; removing the anolyte fluid, anolyte gas, catholyte fluid, and catholyte gas from the vessel; mixing a portion of the anolyte gas with the catholyte fluid to produce ozone gas and hypochlorite bleach mixture; re-circulating the ozone gas with the ozone gas and hypochlorite bleach mixture; mixing the anolyte fluid with the hypochlorite bleach solution; mixing a chlorite brine with the hypochlorite bleach solution to produce a chlorite brine/hypochlorite bleach solution mixture; and mixing the anolyte fluid with the chlorite brine/hypochlorite bleach solution mixture to the produce the biocide.Type: GrantFiled: March 12, 2013Date of Patent: September 20, 2016Assignee: Strategic Resource Optimization, Inc.Inventors: Michael J. Peters, John D. Breedlove, Seth R. Meyer
-
Publication number: 20160044926Abstract: A method for electrolytically generating a biocide, including providing a brine solution carrier fluid; providing a vessel for creating a first passageway and a second passageway, flowing the carrier fluid through the vessel; applying an electric potential to the electrodes to produce an anolyte fluid, an anolyte gas, a catholyte fluid, and a catholyte gas in the vessel; removing the anolyte fluid, anolyte gas, catholyte fluid, and catholyte gas from the vessel; mixing a portion of the anolyte gas with the catholyte fluid to produce ozone gas and hypochlorite bleach mixture; re-circulating the ozone gas with the ozone gas and hypochlorite bleach mixture; mixing the anolyte fluid with the hypochlorite bleach solution; mixing a chlorite brine with the hypochlorite bleach solution to produce a chlorite brine/hypochlorite bleach solution mixture; and mixing the anolyte fluid with the chlorite brine/hypochlorite bleach solution mixture to the produce the biocide.Type: ApplicationFiled: March 12, 2013Publication date: February 18, 2016Inventors: Michael J. Peters, John D. Breedlove, Seth R. Mayer
-
Publication number: 20150373985Abstract: A biocide, including from about 10 parts per million to about 1,000 parts per million of chlorine dioxide; hypochlorite; chlorite salt; and a buffer; wherein the biocide has a pH of from about 4 to about 10 and an oxidation/reduction potential of from about +700 to about +1,200 millivolts.Type: ApplicationFiled: July 9, 2012Publication date: December 31, 2015Applicant: STRATEGIC RESOURCE OPTIMIZATION, INC.Inventors: Michael J. Peters, John D. Breedlove
-
Patent number: 8898517Abstract: An apparatus for handling a failed processor of a multiprocessor system including at least two processors interconnected by processor interconnects for facilitating transactions of the processors. The at least two processors include a first processor set as a default boot processor in response to a boot up operation of the multiprocessor computer, and a second processor. The apparatus includes: a baseboard management module for detecting and receiving health information of the processors; a multiplexer coupled to the baseboard management module and respectively to the processors, the multiplexer being operative to switch between the processors; and a processor ID controller coupled to the baseboard management module and respectively to the processors. In response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management module enables the multiplexer to switch to the second processor.Type: GrantFiled: December 2, 2011Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Yao-Chun Cheng, Yuan-Ning Lien, Chuan Yung Liu, Feng-I Liu, Kuei Huang Liu, Michael J. Peters
-
Patent number: 8892944Abstract: A method for handling a failed processor of a multiprocessor system, the multiprocessor system comprising at least two processors interconnected by processor interconnects for transactions between processors, the processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor system. The method comprises: detecting and receiving, via a baseboard management module, health information of the at least two processors; providing a multiplexer operative to switch between the at least two processors, the multiplexer being coupled to the baseboard management module and respectively to the at least two processors; and, in response to the health information indicating the first processor has failed, setting, via a processor ID controller, the second processor as the default boot processor and enabling, via the baseboard management module, the multiplexer to switch to the second processor.Type: GrantFiled: July 3, 2012Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Yao-Chun Cheng, Yuan-Ning Lien, Chuan Yung Liu, Feng-I Liu, Kuei Huang Liu, Michael J. Peters
-
Patent number: 8394253Abstract: A method for electrolytically generating a biocide having an electron deficient carrier fluid and chlorine dioxide, including providing a carrier fluid; providing a pair of electrodes interposed by a semi-permeable membrane within a vessel for creating a first passageway and a second passageway, an anode electrode of the pair of electrodes disposed in the first passageway, cathode electrode of the pair of electrodes disposed in the second passageway; flowing the carrier fluid through the vessel; applying an electric potential to the pair of electrodes to produce an oxidative acidic fluid, a reductive alkaline fluid, and anodic gases in the container; removing the fluids and gases from the vessel; mixing a portion of the anodic gases with the reductive alkaline fluid to produce a hypochlorite solution; and mixing a chlorite brine with the hypochlorite solution, followed by the introduction of additional oxidative acidic fluid to release the biocide.Type: GrantFiled: November 16, 2010Date of Patent: March 12, 2013Assignee: Strategic Resource Optimization, Inc.Inventors: Michael J. Peters, John D. Breedlove, David D. Faulder, Seth R. Mayer
-
Patent number: 8333883Abstract: An electrolytic method for extracting components from subsurface strata including providing a carrier fluid; providing a pair of electrodes within a container, the container having a first outlet located proximal to a first electrode of the pair of electrodes and a second outlet located proximal to a second electrode of the pair of electrodes; flowing the carrier fluid through the container; applying a potential to the pair of electrodes to produce a first ionized carrier fluid and a second ionized carrier fluid in the container; removing the first ionized carrier fluid from the container through their respective outlets; injecting one of the first ionized carrier fluid and the second ionized carrier fluid into the subsurface strata to release the components; and recovering one of the first ionized carrier fluid and second ionized carrier fluid and components from the subsurface strata.Type: GrantFiled: November 19, 2010Date of Patent: December 18, 2012Assignee: Strategic Resource Optimization, LLCInventors: Michael J. Peters, David D. Faulder
-
Publication number: 20120278653Abstract: A method for handling a failed processor of a multiprocessor system, the multiprocessor system comprising at least two processors interconnected by processor interconnects for transactions between processors, the processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor system. The method comprises: detecting and receiving, via a baseboard management module, health information of the at least two processors; providing a multiplexer operative to switch between the at least two processors, the multiplexer being coupled to the baseboard management module and respectively to the at least two processors; and, in response to the health information indicating the first processor has failed, setting, via a processor ID controller, the second processor as the default boot processor and enabling, via the baseboard management module, the multiplexer to switch to the second processor.Type: ApplicationFiled: July 3, 2012Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yao-Chun Cheng, Yuan-Ning Lien, Chuan Yung Liu, Feng-I Liu, Kuei Huang Liu, Michael J. Peters
-
Publication number: 20120173922Abstract: An apparatus for handling a failed processor of a multiprocessor system including at least two processors interconnected by processor interconnects for facilitating transactions of the processors. The at least two processors include a first processor set as a default boot processor in response to a boot up operation of the multiprocessor computer, and a second processor. The apparatus includes: a baseboard management module for detecting and receiving health information of the processors; a multiplexer coupled to the baseboard management module and respectively to the processors, the multiplexer being operative to switch between the processors; and a processor ID controller coupled to the baseboard management module and respectively to the processors. In response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management module enables the multiplexer to switch to the second processor.Type: ApplicationFiled: December 2, 2011Publication date: July 5, 2012Applicant: International Business Machiness CorporationInventors: Yao-Chun Cheng, Yuan-Ning Lien, Chuan Yung Liu, Feng-I Liu, Kuei Huang Liu, Michael J. Peters
-
Publication number: 20120121731Abstract: A method for electrolytically generating a biocide having an electron deficient carrier fluid and chlorine dioxide, including providing a carrier fluid; providing a pair of electrodes interposed by a semi-permeable membrane within a vessel for creating a first passageway and a second passageway, an anode electrode of the pair of electrodes disposed in the first passageway, cathode electrode of the pair of electrodes disposed in the second passageway; flowing the carrier fluid through the vessel; applying an electric potential to the pair of electrodes to produce an oxidative acidic fluid, a reductive alkaline fluid, and anodic gases in the container; removing the fluids and gases from the vessel; mixing a portion of the anodic gases with the reductive alkaline fluid to produce a hypochlorite solution; and mixing a chlorite brine with the hypochlorite solution, followed by the introduction of additional oxidative acidic fluid to release the biocide.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Inventors: Michael J. Peters, David D. Faulder, John D. Breedlove, S. Robert Mayer
-
Patent number: 8157981Abstract: The present electrolytic system and method for extracting components includes a means for providing a carrier fluid; a means for providing a pair of electrodes interposed by a permeable membrane to create a first channel and a second channel; a means for flowing the carrier fluid through the first and second channel; a means for applying a voltage to the pair of electrodes to produce a first ionized carrier fluid in the first channel and a second ionized carrier fluid in the second channel; a means for injecting at least one of the first ionized carrier fluid and the second ionized carrier fluid into the subsurface reservoir to release the components; and a means for recovering the at least one of the first ionized carrier fluid and the second ionized carrier fluid and the components from a subsurface strata or ex-situ mineral deposit.Type: GrantFiled: November 22, 2006Date of Patent: April 17, 2012Assignee: Strategic Resource Optimization, LLCInventors: Michael J. Peters, David D. Faulder
-
Publication number: 20110062032Abstract: An electrolytic method for extracting components from subsurface strata including providing a carrier fluid; providing a pair of electrodes within a container, the container having a first outlet located proximal to a first electrode of the pair of electrodes and a second outlet located proximal to a second electrode of the pair of electrodes; flowing the carrier fluid through the container; applying a potential to the pair of electrodes to produce a first ionized carrier fluid and a second ionized carrier fluid in the container; removing the first ionized carrier fluid from the container through their respective outlets; injecting one of the first ionized carrier fluid and the second ionized carrier fluid into the subsurface strata to release the components; and recovering one of the first ionized carrier fluid and second ionized carrier fluid and components from the subsurface strata.Type: ApplicationFiled: November 19, 2010Publication date: March 17, 2011Applicant: Strategic Resource Optimization, Inc.Inventors: Michael J. Peters, David D. Faulder
-
Publication number: 20100072059Abstract: The present electrolytic system for decontaminating a contaminant disposed on a substrate includes means for providing a brine solution; means for providing a pair of electrodes interposed by a permeable membrane to create a first channel and a second channel; means for flowing the brine solution through the first and second channel; means for applying a potential to the pair of electrodes to produce a first ionized decontamination solution in the first channel and a second ionized decontamination solution in the second channel; means for applying one of the first ionized decontamination solution and the second decontamination solution to the contaminant; and means for recovering the at least one of the first ionized decontamination solution and the second ionized decontamination solution and the contaminant from the substrate.Type: ApplicationFiled: September 25, 2008Publication date: March 25, 2010Inventors: Michael J. Peters, David D. Faulder, John D. Breedlove
-
Publication number: 20100039346Abstract: An antenna assembly comprises a plurality of antenna elements arranged in an array, and a radome for protecting the antenna elements, wherein the radome has a thickness that changes across a field of view to normalize insertion phase delay differences in an incoming signal passing through the radome and received by the antenna elements.Type: ApplicationFiled: April 21, 2008Publication date: February 18, 2010Applicant: Northrop Grumman CorporationInventors: Michael J. Peter, Peter M. Corcoran
-
Publication number: 20080115930Abstract: The present electrolytic system and method for extracting components includes a means for providing a carrier fluid; a means for providing a pair of electrodes interposed by a permeable membrane to create a first channel and a second channel; a means for flowing the carrier fluid through the first and second channel; a means for applying a voltage to the pair of electrodes to produce a first ionized carrier fluid in the first channel and a second ionized carrier fluid in the second channel; a means for injecting at least one of the first ionized carrier fluid and the second ionized carrier fluid into the subsurface reservoir to release the components; and a means for recovering the at least one of the first ionized carrier fluid and the second ionized carrier fluid and the components from a subsurface strata or ex-situ mineral deposit.Type: ApplicationFiled: November 22, 2006Publication date: May 22, 2008Inventors: Michael J. Peters, David D. Faulder
-
Patent number: 6799293Abstract: A sparse byte enable indicator for high speed memory access arbitration and a memory controller utilizing same is provided. According to the invention, a sparse byte enable indication is provided to the memory controller with or at about the same time that a request for a write to memory is received from a client. In response to receiving the sparse byte enable indication, the memory controller can begin to initiate a read-modify-write sequence. The present invention allows write operations involving less than complete data words in a first block of data to be completed in fewer clock cycles than in connection with controllers that do not utilize a sparse byte enable indication. The present invention is applicable in connection with any device controlling access to memory in systems utilizing error correction code.Type: GrantFiled: June 19, 2001Date of Patent: September 28, 2004Assignee: Adaptec, Inc.Inventors: Michael J. Peters, James R. Klobcar
-
Patent number: 6636927Abstract: The present invention provides bridge device for transferring data using master-specific prefetch sizes. The bridge device is coupled between a first bus and a second bus with the master devices being coupled to the first bus and the slave devices being coupled to the second bus. The bridge device includes a set of prefetch control registers, a prefetch buffer, and bridge control circuitry. The set of prefetch control registers is arranged to store prefetch sizes of data to be prefetched for a set of the master devices with one prefetch control register being provided for a master device. The prefetch buffer is arranged to store data for transfer. The bridge control circuitry is coupled to the prefetch control registers and the prefetch buffer for transferring data between a source device and a destination device.Type: GrantFiled: September 24, 1999Date of Patent: October 21, 2003Assignee: Adaptec, Inc.Inventors: Michael J. Peters, Donald N. Allingham, Patrick R. Bashford
-
Publication number: 20030002466Abstract: A sparse byte enable indicator for high speed memory access arbitration and a memory controller utilizing same is provided. According to the invention, a sparse byte enable indication is provided to the memory controller with or at about the same time that a request for a write to memory is received from a client. In response to receiving the sparse byte enable indication, the memory controller can begin to initiate a read-modify-write sequence. The present invention allows write operations involving less than complete data words in a first block of data to be completed in fewer clock cycles than in connection with conventional controllers that do not utilize a sparse byte enable indication. The present invention is applicable in connection with any device controlling access to memory in systems utilizing error correction code.Type: ApplicationFiled: June 19, 2001Publication date: January 2, 2003Inventors: Michael J. Peters, James R. Klobcar
-
Patent number: 6480817Abstract: A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin.Type: GrantFiled: September 1, 1994Date of Patent: November 12, 2002Assignee: Hynix Semiconductor, Inc.Inventors: Michael J. Peters, Richard L. Collins, David M. Musolf, Patrick R. Bashford, Bradley J. Wright