Abstract: An upstream-communication end node of an apparatus in an example upon a receipt of an indication of threshold-partial fullness of transaction-storage space on a downstream-communication end node modifies transaction-selection for delivery to the downstream-communication end node to exclude one or more transactions originated on the upstream-communication end node.

Abstract: One exemplary method of assigning addresses in two or more address spaces with address fields of different lengths comprises defining address types, assigning a value to first bits at the high ends of the address fields to identify a first said address type, assigning second bits at the low ends of the address fields to identify addresses of the first said address type, and inserting different numbers of additional bits between the first bits and the second bits in the two or more address spaces.

Abstract: An upstream-communication end node of an apparatus in an example upon a receipt of an indication of threshold-partial fullness of transaction-storage space on a downstream-communication end node modifies transaction-selection for delivery to the downstream-communication end node to exclude one or more transactions originated on the upstream-communication end node.

Abstract: One exemplary method of assigning addresses in two or more address spaces with address fields of different lengths comprises defining address types, assigning a value to first bits at the high ends of the address fields to identify a first said address type, assigning second bits at the low ends of the address fields to identify addresses of the first said address type, and inserting different numbers of additional bits between the first bits and the second bits in the two or more address spaces.

Abstract: The present invention relates to a programmable retargeter memory device which receives data being sent to addresses designated by the data and which retargets the data by replacing the addresses designated by the data with new addresses. The retargeter memory device of the present invention comprises an address memory and a data memory. The address memory comprises a plurality of address memory locations for storing retargeted addresses. The address memory is capable of being written to and read from to programmably alter the retargeted addresses stored therein and to output retargeted addresses therefrom. The data memory comprises a plurality of data memory locations for storing data associated with the retargeted addresses stored in the address memory and is capable of being written to and read from.

Abstract: The present invention relates to a programmable retargeter memory device which receives data being sent to addresses designated by said data and which retargets the data by replacing the addresses designated by the data with new addresses. The retargeter memory device of the present invention comprises an address memory and a data memory. The address memory comprises a plurality of address memory locations for storing retargeted addresses. The address memory is capable of being written to and read from to programmably alter the retargeted addresses stored therein and to output retargeted addresses therefrom. The data memory comprises a plurality of data memory locations for storing data associated with the retargeted addresses stored in the address memory and is capable of being written to and read from.

Abstract: A multi-processor graphics system including a general purpose system control processor for setting up the workstation environment and data traversal structures based upon an application model language description. Workload balancing and interprocessor communication is managed by defining a general purpose interface between the general purpose processor and special purpose graphics control processor. The system control processor accepts application program information in a standard form, such as a hierarchical graphics language definition, then converts it into generalized interface control blocks for communication to the graphics control processor. Graphics control processor is signalled by an interrupt from the system control processor to begin the traversal process. The graphics control processor can then access the standard control blocks contained in system memory and perform the traversal necessary to generate the requested graphics image.