Abstract: A wafer stack can be produced by using indium electroplating on physical vapor deposition tantalum. The wafer stack includes a substrate, a tantalum-nitride film formed on the substrate, a tantalum layer formed on the tantalum-nitride film, and indium deposited on the tantalum layer. Various relationships of thicknesses between the tantalum layer and the tantalum-nitride film can be used in producing the wafer stack.

Abstract: A method is provided to fabricate a wafer including a bonding layer interposed between a device wafer and a handle wafer. The method includes performing a first deposition process to deposit an ultraviolet (UV) shield layer on a backside surface of the handle wafer. A second deposition process is performed to deposit a stress compensation layer on an exposed surface of the UV shield layer. The UV shield layer blocks UV energy generated while performing the second deposition process from reaching the bonding layer.

Abstract: A method for fabricating a wafer stack. The method includes forming a tantalum-nitride film on a substrate of the wafer stack using physical vapor deposition, forming a tantalum layer on the tantalum-nitride film using physical vapor deposition, and depositing indium on the tantalum layer using electroplating.

Abstract: Interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

Abstract: Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

Abstract: A semiconductor device includes a substrate with both a compressive layer and an aluminum nitride tensile layer overlying at least a portion of the substrate. The aluminum nitride tensile layer is configured to counteract the compressive layer stress in the device to thereby control an amount of substrate bow in the device. The device includes a temperature-sensitive material supported by the substrate, in which the temperature-sensitive material has a relatively low thermal degradation temperature. The aluminum nitride tensile layer is formed at a temperature below the thermal degradation temperature of the temperature-sensitive material.

Abstract: A method for fabricating a wafer stack. The method includes forming a tantalum-nitride film on a substrate of the wafer stack using physical vapor deposition, forming a tantalum layer on the tantalum-nitride film using physical vapor deposition, and depositing indium on the tantalum layer using electroplating.

Abstract: A method is provided to fabricate a wafer including a bonding layer interposed between a device wafer and a handle wafer. The method includes performing a first deposition process to deposit an ultraviolet (UV) shield layer on a backside surface of the handle wafer. A second deposition process is performed to deposit a stress compensation layer on an exposed surface of the UV shield layer. The UV shield layer blocks UV energy generated while performing the second deposition process from reaching the bonding layer.

Abstract: Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

Abstract: A semiconductor device includes a substrate with both a compressive layer and an aluminum nitride tensile layer overlying at least a portion of the substrate. The aluminum nitride tensile layer is configured to counteract the compressive layer stress in the device to thereby control an amount of substrate bow in the device. The device includes a temperature-sensitive material supported by the substrate, in which the temperature-sensitive material has a relatively low thermal degradation temperature. The aluminum nitride tensile layer is formed at a temperature below the thermal degradation temperature of the temperature-sensitive material.

Abstract: A semiconductor device has a substrate with both compressive and tensile layers deposited overlying a single major surface (face) of the device. The tensile layer may be deposited directly on the substrate of the device, with the compressive layer overlying the tensile layer. A transition material may be located between the tensile layer and the compressive layer. The transition material may be a compound including the components of one or both of the tensile layer and the compressive layer. In a specific embodiment, the tensile material may be a silicon nitride, the compressive layer may be a silicon oxide, and the transition material may be a silicon oxy-nitride, which may be formed by oxidizing the surface of the tensile silicon nitride layer. By depositing both tensile and compressive layers on the same face of the device the opposite major surface (face) is free for processing.

Abstract: A semiconductor device has a substrate with both compressive and tensile layers deposited overlying a single major surface (face) of the device. The tensile layer may be deposited directly on the substrate of the device, with the compressive layer overlying the tensile layer. A transition material may be located between the tensile layer and the compressive layer. The transition material may be a compound including the components of one or both of the tensile layer and the compressive layer. In a specific embodiment, the tensile material may be a silicon nitride, the compressive layer may be a silicon oxide, and the transition material may be a silicon oxy-nitride, which may be formed by oxidizing the surface of the tensile silicon nitride layer. By depositing both tensile and compressive layers on the same face of the device the opposite major surface (face) is free for processing.