Patents by Inventor Michael J. S. Smith

Michael J. S. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10637724
    Abstract: Methods, systems, and computer program products for managing Internet of Things (IoT) network-connected devices.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: April 28, 2020
    Assignee: REMOT3.IT, INC.
    Inventors: Michael W. Johnson, Ryo Koyama, Michael J. S. Smith
  • Patent number: 9712486
    Abstract: A method, system, and computer program product for Internet of Things (IoT) network-connected devices. Embodiments include methods and systems for registering one or more listener devices (e.g., mobile phones or tablets, etc.) to receive messages from one or more notification devices (e.g., web cameras, etc.). A notification server is selected from among multiple notification servers to receive notification messages from the notification devices and then to forward (e.g., through a push service, etc.) portions of or variations of the notification messages to the listener devices. In some embodiments, the selection of the notification server is based on load balancing between the multiple notification servers and/or push servers. In some embodiments, the selection of a notification server and/or push server is based on a provisioning file.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: July 18, 2017
    Assignee: Weaved, Inc.
    Inventors: Michael W. Johnson, Ryo Koyama, Michael J. S. Smith
  • Patent number: 9231904
    Abstract: A method, system, and computer program product for network-connected devices.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: January 5, 2016
    Assignee: Weaved, Inc.
    Inventors: Michael W. Johnson, Ryo Koyama, Michael J. S. Smith
  • Patent number: 8797779
    Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 5, 2014
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael J. S. Smith, David T. Wang, Frederick Daniel Weber
  • Patent number: 8751732
    Abstract: In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 10, 2014
    Assignee: Google Inc.
    Inventors: Radoslav Danilak, Michael J. S. Smith, Suresh Rajan
  • Patent number: 8730670
    Abstract: One embodiment of the present invention sets forth a heat spreader module for dissipating thermal heat generated by electronic components. The assembly comprises a printed circuit board (PCB), electronic components disposed on the PCB, a thermal interface material (TIM) thermally coupled to the electronic components, and a heat spreader plate thermally coupled to the TIM. The heat spreader plate includes an embossed pattern. Consequently, surface area available for heat conduction between the heat spreader plate and surrounding medium may be increased relative to the prior art designs.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: May 20, 2014
    Assignee: Google Inc.
    Inventors: Wael O. Zohni, William Schmidt, Michael J. S. Smith, Jeremy Matthew Plunkett
  • Patent number: 8619452
    Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: December 31, 2013
    Assignee: Google Inc.
    Inventors: Suresh N. Rajan, Michael J. S. Smith, David T Wang
  • Patent number: 8566556
    Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 22, 2013
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael J. S. Smith, David T. Wang, Frederick Daniel Weber
  • Patent number: 8438328
    Abstract: One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.
    Type: Grant
    Filed: February 14, 2009
    Date of Patent: May 7, 2013
    Assignee: Google Inc.
    Inventors: Michael J. S. Smith, Suresh Natarajan Rajan, David T. Wang
  • Publication number: 20130100746
    Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 25, 2013
    Applicant: GOOGLE INC.
    Inventors: Suresh N. Rajan, Michael J. S. Smith, David T. Wang
  • Patent number: 8386833
    Abstract: One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: February 26, 2013
    Assignee: Google Inc.
    Inventors: Michael J. S. Smith, Suresh Natarajan Rajan
  • Patent number: 8370566
    Abstract: In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: February 5, 2013
    Assignee: Google Inc.
    Inventors: Radoslav Danilak, Michael J. S. Smith, Suresh Rajan
  • Publication number: 20120233395
    Abstract: One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 13, 2012
    Applicant: GOOGLE INC.
    Inventors: Michael J. S. Smith, Suresh Natarajan Rajan, David T. Wang
  • Patent number: 8089795
    Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: January 3, 2012
    Assignee: Google Inc.
    Inventors: Suresh N. Rajan, Keith R Schakel, Michael J. S. Smith, David T Wang, Frederick Daniel Weber
  • Patent number: 8055833
    Abstract: In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: November 8, 2011
    Assignee: Google Inc.
    Inventors: Radoslav Danilak, Michael J. S. Smith, Suresh Rajan
  • Patent number: 6326806
    Abstract: An FPGA-based communications access point and system for reconfiguration of the FPGA via a communications channel are described in various embodiments. One embodiment includes a physical interface circuit, a storage element (e.g., a RAM), an FPGA, and a configuration control circuit. The physical interface circuit is arranged for connection to a communications channel and is coupled to the FPGA. The configuration control circuit includes a controlling circuit (e.g., a PLD) and a memory circuit (e.g., a PROM). The PROM is configured with an initial configuration bitstream for the FPGA. The initial configuration bitstream implements both a communications protocol and a control function that writes configuration bits received by the FPGA via the communications channel to the RAM. The control function also generates a reconfiguration signal responsive to a first predetermined condition.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: December 4, 2001
    Assignee: Xilinx, Inc.
    Inventors: Hamish T. Fallside, Michael J. S. Smith
  • Patent number: 5402358
    Abstract: A method for creating a physical layout of an analog integrated circuit characterized by the steps of developing a library of device modules and then assembling the device modules in an iterative fashion to create the desired analog circuit. The iterative process is preferably performed in a computerized spreadsheet program by developing an initial tiling script for the device modules, calculating the operating specifications of the circuit produced by the tiling script, comparing the calculated operating specifications against the desired operating parameters of the circuit and modifying the tiling script and repeating the process until the calculated operating specifications meet the desired operating parameters. In one embodiment the desired operating parameters include operating parameters of the analog circuit taken as a whole and in another embodiment the desired operating parameters include operating parameters of individual devices within the analog circuit.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: March 28, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Michael J. S. Smith, Clemenz L. Portmann