Abstract: A system for power management. The system includes a plurality of input/output pads and a plurality of input/output cells, where each input/output cell is coupled to one of the input/output pads. The system further includes a plurality of interrupt observe circuits, where each interrupt observe circuit is coupled to one of the input/output cells, and where the interrupt observe circuits are configured to generate an interrupt flag during a low power mode.

Abstract: A power-saving block may be isolated from a remainder of a digital circuit. To save power, the power-saving block may be powered down when not in use. To prevent the power-down process from creating metastable states in the remainder of the digital circuit, appropriate isolation gates may separate outputs of the power-saving block from the remainder of the digital circuit. Signals may be sent to the power-saving block to ensure that the output signals from the power-saving block are always the same value during the power-down process. The isolation gates may be chosen based on the value expected on the output signals during the power-down process. Assertions may be used to confirm that the correct isolation gates were selected.

Abstract: A system for power management. The system includes a plurality of input/output pads and a plurality of input/output cells, where each input/output cell is coupled to one of the input/output pads. The system further includes a plurality of interrupt observe circuits, where each interrupt observe circuit is coupled to one of the input/output cells, and where the interrupt observe circuits are configured to generate an interrupt flag during a low power mode.

Abstract: Disclosed herein are various embodiments of an application specific integrated circuit (ASIC). The ASIC includes a plurality of functional units. Each functional unit may include a plurality of connections. The ASIC may also include a plurality of input and/or output pins configured to couple the ASIC to a circuit board. A programmable client may be associated with each pin, and each programmable client may be programmed to selectively connect the pin with which it is associated to one of the plurality of connections of one of the plurality of functional units. In various embodiments, the programmable client may be embodied as a multiplexer or a crossbar switch. Further, the programmable client may be programmed using any of boot firmware, hardware jumpers, and/or non-volatile programming registers.

Abstract: Disclosed is a method of validating the contents of a real-time clock in a digital circuit. A plurality of memory elements create a first random signature value when power is newly applied to a circuit. The plurality of memory elements maintain the first random signature value while power to the circuit is maintained. The first random signature value is stored as a reference value such that the reference value is not altered by a power interruption. When power to the circuit is lost and then regained, a second random signature value is created. The second random signature value likely will no longer match the reference value because both the reference value and the second signature are random. When the reference value does not match the signature value, the real-time clock value is considered invalid. User input may be employed to correct the real-time clock value.

Abstract: A delay lock loop for use in meeting SDRAM timing requirements, wherein a timing relationship between data generated by a computer chip and a clock in said DRAM is fully programmable, and wherein said delay lock loop is digitally implemented. The delay lock loop includes a first delay chain to measure a number of delay taps in a single clock cycle of the clock of the SDRAM and a second delay chain to delay the clock of the SDRAM. The second delay chain is matched to the first delay chain.

Abstract: A graphics controller produces a composite image through selecting between input image pixels, which are designated to be displayed in the same pixel location, by using a select function. The select function is computed on a pixel by pixel basis to provide a select signal that indicates which pixel should be chosen for display as the final composite image on the display screen. The select signal uses mixing key functions to determine which pixel should be passed. The results of these functions are output in the form of key codes. Key codes are combined by performing a logical AND operation between the key codes, and with a Raster OPeration (ROP) code. The ROP code designates which key code combinations are to be logically ORed together to provide an increased number of possible key combinations to determine the selection of the image to be displayed.