Patents by Inventor Michael J. Schulte

Michael J. Schulte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143056
    Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.
    Type: Application
    Filed: July 5, 2023
    Publication date: May 2, 2024
    Inventors: Greg SADOWSKI, Sriram Sundarm, Stephen Kushnir, William C. Brantley, Michael J. Schulte
  • Publication number: 20240095180
    Abstract: The disclosed computer-implemented method for interpolating register-based lookup tables can include identifying, within a set of registers, a lookup table that has been encoded for storage within the set of registers. The method can also include receiving a request to look up a value in the lookup table and responding to the request by interpolating, from the encoded lookup table stored in the set of registers, a representation of the requested value. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 23, 2022
    Publication date: March 21, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Michael Estlick, Jay Fleischman, Michael J. Schulte, Bradford Beckmann, Yasuko Eckert
  • Patent number: 11921784
    Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 5, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Dasika, Michael Ignatowski, Michael J Schulte, Gabriel H Loh, Valentina Salapura, Angela Beth Dalton
  • Patent number: 11709536
    Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 25, 2023
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Greg Sadowski, Sriram Sundaram, Stephen Kushnir, William C. Brantley, Michael J. Schulte
  • Patent number: 11602796
    Abstract: Railway wheel milling tool system including a railway wheel truing cutters and tangential railway wheel milling inserts are disclosed. The tangential milling inserts have at least four indexable cutting edges, each with a central wiper cutting edge segment between two convex cutting edge segments. The milling inserts may allow both the flat portion and curved portion of a railway wheel to be machined with an improved surface finish. The railway wheel truing cutters comprise a plurality of insert pockets structured and arranged to receive the tangential railway wheel milling inserts.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: March 14, 2023
    Assignees: Kennametal Inc., NSH USA Corporation
    Inventors: Michael J. Schulte, Christopher Johnson
  • Publication number: 20220365975
    Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
    Type: Application
    Filed: December 29, 2021
    Publication date: November 17, 2022
    Inventors: Ganesh Dasika, Michael Ignatowski, Michael J. Schulte, Gabriel H. Loh, Valentina Salapura, Angela Beth Dalton
  • Publication number: 20220048120
    Abstract: Railway wheel milling tool system including a railway wheel truing cutters and tangential railway wheel milling inserts are disclosed. The tangential milling inserts have at least four indexable cutting edges, each with a central wiper cutting edge segment between two convex cutting edge segments. The milling inserts may allow both the flat portion and curved portion of a railway wheel to be machined with an improved surface finish. The railway wheel truing cutters comprise a plurality of insert pockets structured and arranged to receive the tangential railway wheel milling inserts.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 17, 2022
    Applicants: Kennametal Inc., Simmons Machine Tool Corporation
    Inventors: Michael J. Schulte, Christopher Johnson
  • Publication number: 20210405722
    Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.
    Type: Application
    Filed: September 23, 2020
    Publication date: December 30, 2021
    Inventors: Greg SADOWSKI, Sriram SUNDARAM, Stephen KUSHNIR, William C. BRANTLEY, Michael J. SCHULTE
  • Patent number: 9804996
    Abstract: Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 31, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James M. O'Connor, Nuwan S. Jayasena, Gabriel H. Loh, Michael Ignatowski, Michael J. Schulte
  • Patent number: 9792961
    Abstract: Various apparatus and methods using phase change materials are disclosed. In one aspect, a method of operating a computing device that has a first semiconductor chip with a first phase change material and a second semiconductor chip with a second phase change material is provided. The method includes determining if the first semiconductor chip phase change material has available thermal capacity. If the first semiconductor chip phase change material has available thermal capacity then the first semiconductor chip is instructed to operate in sprint mode. The first semiconductor chip is instructed to perform a first computing task while in sprint mode.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: October 17, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manish Arora, Nuwan Jayasena, Gabriel H. Loh, Michael J. Schulte, Srilatha Manne
  • Patent number: 9720487
    Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: August 1, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William L. Bircher, Madhu Saravana Sibi Govindan, Manish Arora, Michael J. Schulte, Nuwan S. Jayasena
  • Patent number: 9690350
    Abstract: A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: June 27, 2017
    Assignee: Advances Micro Devices, Inc.
    Inventors: Nam Sung Kim, James M. O'Connor, Michael J. Schulte, Vijay Janapa Reddi
  • Patent number: 9471130
    Abstract: The described embodiments include a computing device with an entity (a processor, a processor core, etc.) and a controller. In these embodiments, the controller, using an idle duration history, predicts a duration of a next idle period for the entity. Based on the predicted duration of the next idle period, the controller configures the entity to operate in a corresponding idle state.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: October 18, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Manish Arora, Nuwan S. Jayasena, Michael J. Schulte
  • Patent number: 9442557
    Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: September 13, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Manish Arora, Nuwan S. Jayasena, Yasuko Eckert, Madhu Saravana Sibi Govindan, William L. Bircher, Michael J. Schulte, Srilatha Manne
  • Patent number: 9360918
    Abstract: A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 7, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Srilatha Manne, Sanjay Pant, Youngtaek Kim, Michael J. Schulte
  • Patent number: 9344091
    Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: May 17, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nuwan S. Jayasena, Michael J. Schulte, Gabriel H. Loh, Michael Ignatowski
  • Patent number: 9331053
    Abstract: Various stacked semiconductor chip arrangements and methods of manufacturing the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip, a second semiconductor chip mounted on the first semiconductor chip, and a first portion of a phase change material positioned in a first pocket associated with the first semiconductor chip or the second semiconductor chip to store heat generated by one or both of the first and second semiconductor chips.
    Type: Grant
    Filed: August 31, 2013
    Date of Patent: May 3, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manish Arora, Nuwan Jayasena, Gabriel H. Loh, Michael J. Schulte
  • Publication number: 20160019937
    Abstract: Various apparatus and methods using phase change materials are disclosed. In one aspect, a method of operating a computing device that has a first semiconductor chip with a first phase change material and a second semiconductor chip with a second phase change material is provided. The method includes determining if the first semiconductor chip phase change material has available thermal capacity. If the first semiconductor chip phase change material has available thermal capacity then the first semiconductor chip is instructed to operate in sprint mode. The first semiconductor chip is instructed to perform a first computing task while in sprint mode.
    Type: Application
    Filed: July 21, 2014
    Publication date: January 21, 2016
    Inventors: Manish Arora, Nuwan Jayasena, Gabriel H. Loh, Michael J. Schulte
  • Patent number: 9235528
    Abstract: A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 12, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lisa R. Hsu, Gabriel H. Loh, Michael Ignatowski, Michael J. Schulte, Nuwan S. Jayasena, James M. O'Connor
  • Patent number: 9218204
    Abstract: A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 22, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: James M. O'Connor, Michael J. Schulte, Nuwan S. Jayasena, Gabriel H. Loh