Abstract: Systems of quickly and easily implanting a quick-connect heart valve prosthesis during a surgical procedure are provided. The heart valve may include a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A system and method for deployment includes an integrated handle shaft and balloon catheter. A safety member disposed between the balloon catheter and handle shaft prevents premature catheter advancement prior to heart valve placement at the annulus, and also may prevent premature balloon inflation prior to full catheter advancement.

Abstract: A quick-connect heart valve prosthesis that can be quickly and easily implanted during a surgical procedure is provided. The heart valve includes a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A small number of guide sutures may be provided for aortic valve orientation. The prosthetic valve may be a commercially available valve with a sewing ring with the frame attached thereto. The frame may expand from a conical deployment shape to a conical expanded shape, and may include web-like struts connected between axially-extending posts. A system and method for deployment includes an integrated handle shaft and balloon catheter. A valve holder is stored with the heart valve and the handle shaft easily attaches thereto to improve valve preparation steps.

Abstract: A quick-connect heart valve prosthesis that can be quickly and easily implanted during a surgical procedure is provided. The heart valve includes a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A small number of guide sutures may be provided for aortic valve orientation. The prosthetic valve may be a commercially available valve with a sewing ring with the frame attached thereto. The frame may expand from a conical deployment shape to a conical expanded shape, and may include web-like struts connected between axially-extending posts. A system and method for deployment includes an integrated handle shaft and balloon catheter. A valve holder is stored with the heart valve and the handle shaft easily attaches thereto to improve valve preparation steps.

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

Abstract: Systems of quickly and easily implanting a quick-connect heart valve prosthesis during a surgical procedure are provided. The heart valve may include a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A system and method for deployment includes an integrated handle shaft and balloon catheter. A safety member disposed between the balloon catheter and handle shaft prevents premature catheter advancement prior to heart valve placement at the annulus, and also may prevent premature balloon inflation prior to full catheter advancement.

Abstract: Methods of quickly and easily implanting a quick-connect heart valve prosthesis during a surgical procedure are provided. The heart valve may include a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A system and method for deployment includes an integrated handle shaft and balloon catheter. A safety member disposed between the balloon catheter and handle shaft prevents premature catheter advancement prior to heart valve placement at the annulus, and also may prevent premature balloon inflation prior to full catheter advancement.

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

Abstract: A quick-connect heart valve prosthesis that can be quickly and easily implanted during a surgical procedure is provided. The heart valve includes a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A small number of guide sutures may be provided for aortic valve orientation. The prosthetic valve may be a commercially available valve with a sewing ring with the frame attached thereto. The frame may expand from a conical deployment shape to a conical expanded shape, and may include web-like struts connected between axially-extending posts. A system and method for deployment includes an integrated handle shaft and balloon catheter. A valve holder is stored with the heart valve and the handle shaft easily attaches thereto to improve valve preparation steps.

Abstract: A quick-connect heart valve prosthesis that can be quickly and easily implanted during a surgical procedure is provided. The heart valve includes a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A small number of guide sutures may be provided for aortic valve orientation. The prosthetic valve may be a commercially available valve with a sewing ring with the frame attached thereto. The frame may expand from a conical deployment shape to a conical expanded shape, and may include web-like struts connected between axially-extending posts. A system and method for deployment includes an integrated handle shaft and balloon catheter. A valve holder is stored with the heart valve and the handle shaft easily attaches thereto to improve valve preparation steps.

Abstract: Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.

Abstract: Methods of quickly and easily implanting a quick-connect heart valve prosthesis during a surgical procedure are provided. The heart valve may include a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A system and method for deployment includes an integrated handle shaft and balloon catheter. A safety member disposed between the balloon catheter and handle shaft prevents premature catheter advancement prior to heart valve placement at the annulus, and also may prevent premature balloon inflation prior to full catheter advancement.

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

Abstract: Methods of quickly and easily implanting a quick-connect heart valve prosthesis during a surgical procedure are provided. The heart valve may include a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A system and method for deployment includes an integrated handle shaft and balloon catheter. A safety member disposed between the balloon catheter and handle shaft prevents premature catheter advancement prior to heart valve placement at the annulus, and also may prevent premature balloon inflation prior to full catheter advancement.

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

Abstract: A system and method for providing backup recovery from outage at a primary gateway in a satellite communication system. Upon detecting an alert indicative of an outage, communication between the primary gateway and a plurality of terminals located within spot beams serviced by the primary gateway is suspended. A pre-switchover routine is performed to initialize a backup gateway capable of being substituted for the primary gateway, and a switchover routine is performed to transfer operations from the primary gateway to the backup gateway. Communication is subsequently enabled between the backup gateway and the plurality of terminals.

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

Abstract: Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.

Abstract: A system comprises a modem, configured to transmit data modulated based on an intermediate frequency within one of a C, X, or Ku band, and a single-stage block-up converter having an input electrically coupled via one inter-facility link cable to the modem, and an output electrically coupled to a high-power amplifier. The single-stage block-up-converter is configured to up-convert the intermediate frequency to a satellite communication frequency within the Ka, Q, or V band.