Abstract: Mechanisms for use on designated ports in spanning tree protocol entities allow such ports to transition to a forwarding state on the basis of actual communication delays between neighboring bridges, rather than upon expiration of forwarding delay timers. The logic that manages transition of states in the spanning tree protocol entity identifies ports which are changing to a designated port role, and issues a message on such ports informing the downstream port that the issuing port is able to assume a forwarding state. The logic begins the standard delay timer for entry to the listening state and then the learning state, prior to assuming the forwarding state. However, when a reply from the downstream port is received, then the issuing port reacts by changing immediately to the forwarding state without continuing to await expiration of the delay timer and without traversing transitional listening and learning states.

Abstract: A method for configuring a network, and a network configured according to such method, are provide in which a communication links laid out in a ring in a metropolitan area are partitioned into link segments, and managed according to a spanning tree protocol. The switches are configured to establish unique, mesh or tree type network configurations suitable for application to communication media arranged to support ring-based protocols. The method is used for connecting communication links arranged in a plurality of rings, which traverse a plurality of collocation sites in a metropolitan area. The method comprises configuring switches in the plurality of collocation sites to partition rings in the plurality of rings into a plurality of link segments providing point to point paths between switches at collocation sites in the plurality of collocation sites. The switches and link segments are managed according to a spanning tree protocol.

Abstract: Mechanisms for use on designated ports in spanning tree protocol entities allow such ports to transition to a forwarding state on the basis of actual communication delays between neighboring bridges, rather than upon expiration of forwarding delay timers. The logic that manages transition of states in the spanning tree protocol entity identifies ports which are changing to a designated port role, and issues a message on such ports informing the downstream port that the issuing port is able to assume a forwarding state. The logic begins the standard delay timer for entry to the listening state and then the learning state, prior to assuming the forwarding state. However, when a reply from the downstream port is received, then the issuing port reacts by changing immediately to the forwarding state without continuing to await expiration of the delay timer and without traversing transitional listening and learning states.

Abstract: A point to multipoint communication channel in a metropolitan area network among a plurality of demarcation points having unique addresses is provided, which includes identifying a particular demarcation point as a root of the channel, and a plurality of client demarcation points as leaves of the channel; and configuring so that client demarcation points can only exchange packets with the root demarcation point, and not with other client demarcation points; and so that the root demarcation point can exchange packets with the plurality of client demarcation points. The channel is managed using source address filtering at switches on the leaves of the channel and a switch at the root of the channel.

Abstract: A method for configuring a network, and a network configured according to such method, provide resilient, redundant connection to an edge device. The system, while not allowing the edge device to participate in the active topology of the network, chooses the active link from the edge device to the network on the basis of the spanning tree information received by the device, but does not allow it to forward or generate spanning tree information. The method manages the redundant connections of an edge device between a first network and a second network, where the second network is managed according to a spanning tree protocol in which spanning tree configuration messages propagate among switches in the second network. The redundant connections are made via a plurality of ports on the edge device coupled to the second network.

Abstract: A method for configuring a network, and a network configured according to such method, are provide in which a communication links laid out in a ring in a metropolitan area are partitioned into link segments, and managed according to a spanning tree protocol. The switches are configured to establish unique, mesh or tree type network configurations suitable for application to communication media arranged to support ring-based protocols. The method is used for connecting communication links arranged in a plurality of rings, which traverse a plurality of collocation sites in a metropolitan area. The method comprises configuring switches in the plurality of collocation sites to partition rings in the plurality of rings into a plurality of link segments providing point to point paths between switches at collocation sites in the plurality of collocation sites. The switches and link segments are managed according to a spanning tree protocol.

Abstract: A communication technique for high volume connectionless-protocol, backbone communication links in distributed processing systems provides for control of latency and reliability of messages transmitted. The system provides for transmit list and receive list processes in the processors on the link. On the transmit side, a high priority command list and a normal priority command list are provided. In the message passing process, the command transmit function transmits commands across the backplane according to a queue priority rule that allows for control of transmit latency. Messages that require low latency are written into the high priority transmit list, while a majority of messages are written into the high throughput or normal priority transmit list. A receive filtering process in the receiving processor includes dispatch logic which dispatches messages either to a high priority receive list or a normal priority receive list.

Abstract: A high performance scalable networking bridge/router system is based on a backbone communication medium and message passing process which interconnects a plurality of input/output modules. The input/output modules vary in complexity from a simple network interface device having no switching or routing resources on board, to a fully functional bridge/router system. Also, in between these two extremes input/output modules which support distributed protocol processing are supported. A central internetworking engine includes a shared memory resource coupled to the backbone.

Abstract: Resources for computing an active network topology in a system having a plurality of ports coupled to respective local area networks include a protocol entity coupled to the plurality of ports which communicates with protocol entities in other systems on the networks to establish the active network topology. Port state logic, coupled with the protocol entity and the plurality of ports establishes active network states for the plurality of ports. The active network states include a first network state for forwarding data and a second network state for blocking data, wherein a transition from a first network state to a second network state is executed after receiving information from the protocol entity indicating a change to the second network state.

Abstract: In an apparatus in a computer network, message filtering proceeds by generating respective class specifiers from a received message, using the message source field, message destination field, and type of message field. The class specifiers are used for generating a class specification, and a domain class is generated from the class specification. A domain list is generated to provide a list of ports to which a message directed to the domain class is to be forwarded. The message is forwarded to the ports listed in the domain list. The apparatus may be a bridge, router, etc.

Abstract: A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.

Abstract: A system uses a message passing paradigm for transferring large amounts of input/output data among a plurality of processors, such as a network intermediate system or router. A bus interconnects the plurality of processors with a plurality of bus interface devices. The bus interface device which originates a transfer includes a command list storing lists of commands which characterize transfers of data messages from local memory across the bus and a packing buffer which buffers the data subject of the command being executed between local memory and the bus. A bus interface device which receives a transfer includes a free buffer list storing pointers to free buffers in local memory into which the data may be loaded from the bus, and a receive list storing pointers to buffers in local memory loaded with data from the bus. The command list includes a first high priority command list and a second lower priority command list for managing latency of the higher priority commands in the software of the processor.

Abstract: DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory.

Abstract: A packet forwarding node for a computer network comprises at least one receiving module and at least one output module including packet list (21) for maintaining a list of packets to be transmitted therefrom. The time for which a packet remains in the node is determined by grouping the packets into groups or "buckets" which are created at regular intervals, each bucket containing packets arriving within the same time interval, and keeping track of the age of each bucket. A bucket counter (33) counts the total number of buckets in existence, so indicating the age of the oldest packet. This counter is incremented by 1 at regular intervals and decremented by 1 each time the oldest bucket is emptied (or found to be empty). A bucket list shift register (30) has its contents shifted at each change of time interval, and its the bottom stage accumulates the number of packets arriving in a time interval, and an overflow accumulator (31) accumulates counts shifted out of its top end.

Abstract: DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory.

Abstract: A reverse address resolution protocol for use in a communication network which allows resolution logic to provide a higher level protocol information (such as an IP address) to a source of a request for such information, independent of the physical network address of such source. The protocol is used in a processor having a plurality of ports, at least one of such ports connected by a point-to-point channel to a remote network device. Reverse address resolution protocol is responsive to a resolution request from the remote network device across the point-to-point channel to supply the higher level protocol information based upon the port through which the resolution request is received, rather than the physical network address of the requesting device. Thus, a remote device may be coupled to a network, and connected to a central management site across a point-to-point communication link, in a "plug and play" mode.

Abstract: The present invention provides an interlock scheme for use between a line card and an address recognition apparatus. The interlock scheme reduces the total number of read/write operations over a backplane bus coupling the line card to the address recognition apparatus required to complete a request/response transfer. Thus, the line card and address recognition apparatus are able to perform a large amount of request/response transfers with a high level of system efficiency. Generally, the interlocking scheme according to the present invention merges each ownership information storage location into the location of the request/response memory utilized to store the corresponding request/response pair to reduce data transfer traffic over the backplane bus. According to another feature of the interlock scheme of the present invention, each of the line card and the address recognition engine includes a table for storing information relating to a plurality of database specifiers.

Abstract: The present invention is directed to an address recognition apparatus including an address recognition engine coupled to a look-up database. The look-up database is arranged to store network information relating to network addresses. The look-up database includes a primary database and a secondary database. The address recognition engine accepts as an input a network address for which network information is required. The address recognition engine uses the network address as an index to the primary database. The primary database comprises a multiway tree node structure (TRIE) arranged for traversal of the nodes as a function of preselected segments of the network address and in a fixed sequence of the segments to locate a pointer to an entry in the secondary database. The entry in the secondary database pointed to by the primary database pointer contains the network information corresponding to the network address. The address recognition engine includes a table for storing a plurality of database specifiers.

Abstract: A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.

Abstract: An error detection scheme to detect a variety of errors, including buffer accesses errors, buffer ownership transfer errors, and address recognition engine access errors, that may occur during the passing of messages between processors in a multi-processor computer system implementing a buffer swapping scheme. The error detection scheme of the present invention provides for the monitoring of bus transactions, maintaining a log of bus activity including buffer access transactions, identifying transactions involving buffer and address recognition operations and checking those operations to insure that they are consistent with the implemented buffer swapping scheme. Upon detection of an error the bus monitoring device asserts an error signal, freezes the log of bus activity and halts buffer swapping activity until the detected error is investigated and dealt with in an appropriate manner.