Patents by Inventor Michael J. Shapiro
Michael J. Shapiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130688Abstract: This relates to methods for measuring irregularities in a signal and corresponding devices. The devices can include a PPG sensor unit configured to detect multiple occurrences of a given event in the measured signal(s) over a sampling interval. In some instances, the device can register the occurrences of the events. In some examples, the device can include one or more motion sensors configured to detect whether the device is in a low-motion state. The device may delay initiating measurements when the device is not in a low-motion state to enhance measurement accuracy. Examples of the disclosure further include resetting the sample procedure based on one or more factors such as the number of non-qualifying measurements. In some examples, the device can be configured to perform both primary and secondary measurements, where the primary measurements can include readings using a set of operating conditions different from the secondary measurements.Type: ApplicationFiled: September 27, 2023Publication date: April 25, 2024Inventors: Stephen J. Waydo, Christopher J. Brouse, Ian R. Shapiro, Joseph C. McBride, Michael O'Reilly, Myra Mary Haggerty
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Patent number: 11163850Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted over a communication link in response to the request.Type: GrantFiled: April 6, 2020Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Robert H. Bell, Jr., Louis B. Capps, Jr., Daniel M. Dreps, Luis A. Lastras-Montano, Michael J. Shapiro
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Publication number: 20200233909Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted over a communication link in response to the request.Type: ApplicationFiled: April 6, 2020Publication date: July 23, 2020Inventors: Robert H. Bell, JR., Louis B. Capps, JR., Daniel M. Dreps, Luis A. Lastras-Montano, Michael J. Shapiro
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Patent number: 10635736Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted to the processor unit instead of the requested data as a response to the read request, and the processor unit replaces the pattern tag with the corresponding data pattern.Type: GrantFiled: January 27, 2018Date of Patent: April 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Bell, Louis B. Capps, Daniel M. Dreps, Luis A. Lastras-Montano, Michael J. Shapiro
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Patent number: 10398044Abstract: An apparatus includes a particle trap coupled to a first surface of an enclosure, wherein the first surface of the enclosure is opposite a top surface of a circuit board. A particle guard coupled to the top surface on a first side of the circuit board located in the enclosure, wherein the enclosure includes one or more apertures on a second surface of the enclosure where the first side of the circuit board is introduced to an external airflow.Type: GrantFiled: October 5, 2018Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Michael J. Shapiro, Brian C. Twichell, Brent W. Yardley
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Publication number: 20190037718Abstract: An apparatus includes a particle trap coupled to a first surface of an enclosure, wherein the first surface of the enclosure is opposite a top surface of a circuit board. A particle guard coupled to the top surface on a first side of the circuit board located in the enclosure, wherein the enclosure includes one or more apertures on a second surface of the enclosure where the first side of the circuit board is introduced to an external airflow.Type: ApplicationFiled: October 5, 2018Publication date: January 31, 2019Inventors: Michael J. Shapiro, Brian C. Twichell, Brent W. Yardley
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Patent number: 10136532Abstract: An apparatus for a dust guard structure includes a particle guard coupled to a top surface of a circuit board, wherein the particle guard is located along a first side of the circuit board between an edge of the circuit board and a first electronic component. The dust guard structure further includes the first electronic component electrically coupled to the circuit board via one or more electronic connections, wherein a height of the particle guard is greater than a height of each of the one or more electrical connections of the first electronic component. The dust guard structure further includes the first side of the circuit board being introduced to an external airflow.Type: GrantFiled: February 17, 2017Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: Michael J. Shapiro, Brian C. Twichell, Brent W. Yardley
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Publication number: 20180242467Abstract: An apparatus for a dust guard structure includes a particle guard coupled to a top surface of a circuit board, wherein the particle guard is located along a first side of the circuit board between an edge of the circuit board and a first electronic component. The dust guard structure further includes the first electronic component electrically coupled to the circuit board via one or more electronic connections, wherein a height of the particle guard is greater than a height of each of the one or more electrical connections of the first electronic component. The dust guard structure further includes the first side of the circuit board being introduced to an external airflow.Type: ApplicationFiled: February 17, 2017Publication date: August 23, 2018Inventors: Michael J. Shapiro, Brian C. Twichell, Brent W. Yardley
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Multicore processor and method of use that configures core functions based on executing instructions
Patent number: 10025590Abstract: A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.Type: GrantFiled: November 23, 2016Date of Patent: July 17, 2018Assignee: International Business Machines CorporationInventors: Louis B. Capps, Jr., Ronald E. Newhart, Thomas E. Cook, Robert H. Bell, Jr., Michael J. Shapiro -
Patent number: 10004154Abstract: An apparatus for a dust guard structure includes a particle guard coupled to a top surface of a circuit board, wherein the particle guard is located along a first side of the circuit board between an edge of the circuit board and a first electronic component. The dust guard structure further includes the first electronic component electrically coupled to the circuit board via one or more electronic connections, wherein a height of the particle guard is greater than a height of each of the one or more electrical connections of the first electronic component. The dust guard structure further includes the first side of the circuit board being introduced to an external airflow.Type: GrantFiled: October 2, 2017Date of Patent: June 19, 2018Assignee: International Business Machines CorporationInventors: Michael J. Shapiro, Brian C. Twichell, Brent W. Yardley
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Publication number: 20180165377Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted to the processor unit instead of the requested data as a response to the read request, and the processor unit replaces the pattern tag with the corresponding data pattern.Type: ApplicationFiled: January 27, 2018Publication date: June 14, 2018Inventors: Robert H. Bell, JR., Louis B. Capps, JR., Daniel M. Dreps, Luis A. Lastras-Montano, Michael J. Shapiro
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Patent number: 9881099Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.Type: GrantFiled: May 24, 2010Date of Patent: January 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Danie M. Dreps, Luis A Lastras-Montano, Michael J Shapiro
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Patent number: 9852959Abstract: The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.Type: GrantFiled: February 5, 2016Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: John A. Fitzsimmons, Michael J. Shapiro, Natalia Borjemscaia, Vincent McGahay
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Patent number: 9812404Abstract: The disclosure generally relates to semiconductor structures and, more particularly, to electrical connections used with crackstop structures and methods of manufacture. The structure includes: a conductive material; a dielectric material formed over the conductive material; a non-corrosive conductive material in at least one opening of the dielectric material and in direct contact with the conductive material; a crackstop structure formed over the dielectric material; and at least one of wiring layer in contact with the non-corrosive conductive material.Type: GrantFiled: December 30, 2015Date of Patent: November 7, 2017Assignee: GLOBALFOUNDRIES INCInventors: Michael J. Shapiro, John A. Fitzsimmons, Natalia Borjemscaia
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Publication number: 20170229362Abstract: The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.Type: ApplicationFiled: February 5, 2016Publication date: August 10, 2017Inventors: John A. Fitzsimmons, Michael J. Shapiro, Natalia Borjemscaia, Vincent McGahay
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Publication number: 20170194265Abstract: The disclosure generally relates to semiconductor structures and, more particularly, to electrical connections used with crackstop structures and methods of manufacture. The structure includes: a conductive material; a dielectric material formed over the conductive material; a non-corrosive conductive material in at least one opening of the dielectric material and in direct contact with the conductive material; a crackstop structure formed over the dielectric material; and at least one of wiring layer in contact with the non-corrosive conductive material.Type: ApplicationFiled: December 30, 2015Publication date: July 6, 2017Inventors: Michael J. Shapiro, John A. Fitzsimmons, Natalia Borjemscaia
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Multicore Processor and Method of Use That Configures Core Functions Based on Executing Instructions
Publication number: 20170075690Abstract: A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.Type: ApplicationFiled: November 23, 2016Publication date: March 16, 2017Inventors: Louis B. Capps, JR., Ronald E. Newhart, Thomas E. Cook, Robert H. Bell, JR., Michael J. Shapiro -
Multicore processor and method of use that configures core functions based on executing instructions
Patent number: 9507640Abstract: A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.Type: GrantFiled: December 16, 2008Date of Patent: November 29, 2016Assignee: International Business Machines CorporationInventors: Louis B. Capps, Jr., Ronald E. Newhart, Thomas E. Cook, Robert H. Bell, Jr., Michael J. Shapiro -
Publication number: 20150371763Abstract: Some examples describe a first helical electromagnetic coil of a transformer. In some instances, at least a portion of the first helical electromagnetic coil is inside a first semi-conductive substrate. Further, in some examples, the first helical electromagnetic coil has a shape with an internal space. Further, some examples describe a second helical electromagnetic coil of the transformer. In some instances, at least a portion of the second helical electromagnetic coil is nested within the internal space of the first helical electromagnetic coil. Further, in some examples, the at least the portion of the second electromagnetic coil is inside the first semi-conductive substrate.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: Rachel Gordin, WAN NI, Michael J. Shapiro, William F. Van Duyne
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Publication number: 20150371764Abstract: Some examples describe a first helical structure of an electromagnetic inductor coil. In some examples, at least a portion of the first helical structure of the electromagnetic inductor coil is inside a first substrate. Further, some examples describe a second helical structure of the electromagnetic inductor coil. In some instances, at least a portion of the second helical structure is nested within the first helical structure of the electromagnetic inductor coil. Further, in some examples, the at least the portion of the second helical structure is inside the first substrate.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: Rachel Gordin, WAN NI, Michael J. Shapiro, William F. Van Duyne