Abstract: An enable circuit receives an input enable signal that is referenced to a first voltage and generates a level-shifted output enable signal referenced to a second voltage. Bias control circuitry prevents shoot-through currents during ramping of the first voltage and from causing indeterminate logic levels of the level-shifted output enable signal. An enabled level-shifting circuit receives an input logic signal that is referenced to the first voltage and generates a level-shifted output logic signal referenced to the second voltage. Enable circuitry operates in response to the level-shifted output enable signal to enable normal level-shifting operation while the first and second voltages are at normal operating levels and prevents shoot-through currents in the enabled level-shifting circuit from causing indeterminate levels of the level-shifted output logic signal.

Abstract: Charge pump circuitry (1) includes a master charge pump (2) including a voltage multiplier (5) and charge pump (30) which operate to produce a boosted, unregulated voltage (Vunreg), and also includes a slave charge pump (3) including a voltage multiplier (36) and charge pump (50) which operate to produce a boosted control voltage (Vctl) which then is filtered. The boosted, unregulated voltage (Vunreg) is regulated in response to the filtered, boosted control voltage (Vctl) to produce a boosted, regulated, low-noise voltage (Vreg). The boosted control voltage (Vctl), relative to a reference voltage (Vref_SH), is controlled by feedback circuitry (61,62,65) in response to the boosted, regulated, low-noise voltage (Vreg).

Abstract: Charge pump circuitry (1) includes a master charge pump (2) including a voltage multiplier (5) and charge pump (30) which operate to produce a boosted, unregulated voltage (Vunreg), and also includes a slave charge pump (3) including a voltage multiplier (36) and charge pump (50) which operate to produce a boosted control voltage (Vctl) which then is filtered. The boosted, unregulated voltage (Vunreg) is regulated in response to the filtered, boosted control voltage (Vctl) to produce a boosted, regulated, low-noise voltage (Vreg). The boosted control voltage (Vctl), relative to a reference voltage (Vref_SH), is controlled by feedback circuitry (61,62,65) in response to the boosted, regulated, low-noise voltage (Vreg).

Abstract: An oscillator includes oscillator circuitry (8) including a transconductance stage (2) and a resonator (3). A comparator (10) produces first (CLK) and second (/CLK) clock signals which indicate the timing of positive and negative phases of a differential output signal (VIN+?VIN?) produced by the transconductance circuit in response to the resonator. A synchronous rectifier (14) converts the differential output signal to a current (IRECT) in response to the first and second clock signals. A switched capacitor notch filter (15) filters the current in response to the first and second clock signals. A control current (ICONTROL) which controls the transconductance of the transconductance circuit is generated in response to the notch filter. The resonator may be a MEMS resonator.

Abstract: An oscillator includes oscillator circuitry (8) including a transconductance stage (2) and a resonator (3). A comparator (10) produces first (CLK) and second (/CLK) clock signals which indicate the timing of positive and negative phases of a differential output signal (VIN+-VIN?) produced by the transconductance circuit in response to the resonator. A synchronous rectifier (14) converts the differential output signal to a current (IRECT) in response to the first and second clock signals. A switched capacitor notch filter (15) filters the current in response to the first and second clock signals. A control current (ICONTROL) which controls the transconductance of the transconductance circuit is generated in response to the notch filter. The resonator may be a MEMS resonator.

Abstract: A driver circuit implemented in an integrated circuit for driving an output node, typically connected to another integrated circuit. The driver circuit includes a control section which produces a digital control output indicative of the state of the process used to manufacture the integrated circuit. One or more driver sections, each connected to an output node of the integrated circuit, receive the digital control output and use the output to control the state of a transistor array connected between the associated output node and circuit common. The transistor array includes an offset transistor having a channel width to channel length ratio Wo/Lo and a multiplicity of adjust transistors, designated first through N, having respective channel width to channel length ratios (Wa/La)N approximately equal to (Wo/Lo) (1+&Dgr;)N where &Dgr; is a fixed weighted value less than one, such as 0.1.

Abstract: An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions.

Abstract: An input/output buffer including a bidirectional node, an output stage, an input stage, and a control circuit. The output stage has a first n-channel transistor coupled between the bidirectional node and a voltage supply node for pulling-up the bidirectional node, and first and second p-channel transistors coupled between the bidirectional node and the voltage supply node for pulling-up the bidirectional node. The input stage has a first inverter stage coupled between the bidirectional node and a first intermediate node and a second inverter stage coupled between the bidirectional node and a second intermediate node. The input stage also has a second n-channel transistor coupled between the first intermediate node and a ground node and a third n-channel transistor coupled between the second intermediate node and the ground node. The control circuit is coupled to the output stage and to the input stage and enables the output stage when in an output mode and disables the output stage when in an input mode.

Abstract: The present invention is embodied in a Secured Processing Unit (SPU) chip, a microprocessor designed especially for secure data processing. By integrating keys, encryption/decryption engines and algorithms in the SPU, the entire security process is rendered portable and easily distributed across physical boundaries. The invention is based on the orchestration of three interrelated systems: (i) detectors, which alert the SPU to the existence, and help characterize the nature, of a security attack; (ii) filters, which correlate the data from the various detectors, weighing the severity of the attack against the risk to the SPU's integrity, both to its secret data and to the design itself; and (iii) responses, which are countermeasures, calculated by the filters to be most appropriate under the circumstances, to deal with the attack or attacks present.

Abstract: A voltage level triggered ESD protection circuit is immune to standard signal transitions up to approximately 5.5 volts, does not consume any DC current either in the powered up or powered down states, and is interfaceable to a live bus when the system it is connected to is powered down. The trigger circuit is reliably immune to tripping from applied fast bus transitions on a powered-down integrated circuit. The trigger signal is generated in response to sensing both a voltage transition and to reaching a voltage set point such as 7 volts, rather than merely triggering off the voltage transition.

Abstract: A tristate driver interfaces a 3.3 volt digital circuit to a bus that supports both 3.3 and 5.0 volt digital signals. In one embodiment, the pullup circuit path includes a P-channel MOSFET which is backgated by a backgate voltage generator and gated by a gate voltage generator that receives its drive voltage from a comparator and is controlled by an enable circuit. The pulldown circuit path includes an N-channel MOSFET which is controlled by the enable circuit. Current leakage through the pullup circuit is minimized when overvoltage occurs on the bus by suitably gating and backgating the pullup MOSFET. In another embodiment, two MOSFETs are used in the pullup circuit. Both are backgated by a backgate voltage generator, while one is gated by a gate voltage generator that receives its drive voltage from the bus while the other is controlled by an enable circuit. The pulldown circuit path includes an N-channel MOSFET which is controlled by the enable circuit.

Abstract: The present invention provides in some embodiments output buffers and input/output buffers which block the charge leakage from the bus to the internal power supply when the bus voltage exceeds in magnitude the internal power supply voltage or when the module is powered down. This functionality is achieved as follows in some embodiments. A PMOS isolation transistor is connected in series with a pull-up transistor between the internal power supply and the buffer output terminal connected to the bus. The gate of the isolation transistor is connected through a PMOS transistor P to the output terminal and through an NMOS transistor N to ground. The gates of transistors P and N are connected to each other. When the driver is enabled and the pull-up transistor is on, the gates of transistors P and N are high. Transistor P is therefore off. Transistor N is on grounding the gate of the isolation transistor. The isolation transistor turns on allowing the pull-up transistor to drive the output terminal.

Abstract: A CMOS power-up reset circuit provides a power-up output signal, useful to external circuits, when an applied power supply voltage exceeds a first predetermined value, and includes a ratioed transistor divider to generate a voltage on a sensing node which is a portion of the power supply voltage during a power-up transient. The circuit regeneratively latches when the rising power supply voltage and the sensing node voltage differ by more than a second predetermined value, such as a P-channel threshold voltage. A feedback signal subsequently disables current flow through the power-up reset circuit to virtually eliminate static power dissipation, and the power-up output signal is generated. Circuit provisions are incorporated to prevent capacitive coupling from the rising power supply voltage, through the N-wells of the P-channel transistors, to critical internal circuit nodes.