Abstract: A self-configuring memory subsystem for a computer system allows the insertion of memory modules into any of the available expansion sockets without the need for setting switches or inserting the modules in a predefined or restricted sequence and without the requirement of additional logic circuitry or microcode in the computer. Each of the memory modules utilized with the subsystem has a number of size identification bits, each bit being connected to a known value, such as ground or left floating. The size bits are detected by logic circuitry embodied in a programmable logic device (PLD) so that the total memory space may be properly mapped. The PLD is programmed so that it uses the identification bits to "map" the installed memory modules into the logical memory address space as accessed by the memory controller so that each memory location of the memory modules has an allocated memory location without addressing ambiguities.

Abstract: A terminal controller system is described wherein several feature cards are plugged into slots on a board, and I/O signal cables are connected between cards and/or remote multiplexors or terminals. A special purpose card identification (ID) bus is driven by the feature cards and received by an ID adapter. The ID adapter has one select line running to each of the slots on the board. The ID adapter enables the select lines one at a time, whereby the selected feature cards drive their IDs onto the ID bus. A processor records the slot population by ID and also can analyze the IDs to determine if a valid configuration exists. The processor then performs a wrap test on each of its ports. This test alters the ID which it wraps and by comparison with the IDs recorded originally, this enables the processor to logically establish the physical link to particular cards connected to the ports.