Patents by Inventor Michael J. Torla
Michael J. Torla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11546370Abstract: Methods and systems are disclosed for anti-replay protection for network packet communications. A scorecard is stored that includes packet sequence numbers for received packets associated with a network packet flow. For each received packet, an anti-replay unit accesses the scorecard for an initial check to determine if the current packet represents a late packet and/or a replay packet. After further processing, the anti-replay unit accesses the scorecard for a final check to determine if the current packet represents a replay packet. For one embodiment, the initial check uses a first window of packet sequence numbers, and the final check uses a second window of packet sequence numbers that is larger than the first window. For further embodiments, multiple processing units operate in parallel to process received packets and to share the anti-replay unit, and each processing unit requests initial and final checks for received packets it processes.Type: GrantFiled: January 31, 2018Date of Patent: January 3, 2023Assignee: NXP USA, Inc.Inventors: Steve D. Millman, Michael J. Torla, David Abdoo
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Publication number: 20190238585Abstract: Methods and systems are disclosed for anti-replay protection for network packet communications. A scorecard is stored that includes packet sequence numbers for received packets associated with a network packet flow. For each received packet, an anti-replay unit accesses the scorecard for an initial check to determine if the current packet represents a late packet and/or a replay packet. After further processing, the anti-replay unit accesses the scorecard for a final check to determine if the current packet represents a replay packet. For one embodiment, the initial check uses a first window of packet sequence numbers, and the final check uses a second window of packet sequence numbers that is larger than the first window. For further embodiments, multiple processing units operate in parallel to process received packets and to share the anti-replay unit, and each processing unit requests initial and final checks for received packets it processes.Type: ApplicationFiled: January 31, 2018Publication date: August 1, 2019Inventors: Steve D. Millman, Michael J. Torla, David Abdoo
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Patent number: 9158499Abstract: Embodiments of an electronic circuit comprise a module, such as a security module, configured to perform cryptographic processing for a predetermined security protocol that includes random number checking. The security module is controlled by a descriptor that includes instructions that cause the security module to access a generated random number, compare the generated random number to a random number stored during a previous execution of the descriptor, and generate an error signal when the generated random number and the previous execution random number are equal.Type: GrantFiled: April 30, 2012Date of Patent: October 13, 2015Assignee: FREESCALE SEMICONDUCTOR, INCInventors: Michael J. Torla, Steven D. Millman, Thomas E. Tkacik, Frank James
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Publication number: 20130290792Abstract: Embodiments of an electronic circuit comprise a module, such as a security module, configured to perform cryptographic processing for a predetermined security protocol that includes random number checking. The security module is controlled by a descriptor that includes instructions that cause the security module to access a generated random number, compare the generated random number to a random number stored during a previous execution of the descriptor, and generate an error signal when the generated random number and the previous execution random number are equal.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Inventors: Michael J. Torla, Steven D. Millman, Thomas E. Tkacik, Frank James
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Patent number: 7970128Abstract: A technique for producing a hashed output of an input message according to any number of hash algorithms (e.g. SHA-256, SHA-348, SHA-512) having varying bit widths is described. At least a portion of the input message is stored in a first group of registers each having a bit width equal to a first bit width (e.g. 32 bits). If the selected hash algorithm has a larger bit width (e.g. 64 bits), a remainder of the input message is stored in a second plurality of registers each having a bit width equal to the first bit width. The hashed output is then computed according to the selected hash algorithm.Type: GrantFiled: July 20, 2007Date of Patent: June 28, 2011Assignee: Freescale Semiconductor, Inc.Inventor: Michael J. Torla
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Patent number: 7917831Abstract: A result value, such as a parity value, for a set of corresponding data elements from a plurality of storage devices is determined using a commutative operation. When accessing the set of corresponding data elements from a plurality of storage devices, a dual access can be performed for the storage device accessed last for the set of corresponding data elements so as to also obtain a data element from the last-accessed storage device for the next parity calculation. As a result, the number of storage device accesses can be reduced compared to conventional systems whereby a single access is performed for each storage device to obtain a single data element from the storage device.Type: GrantFiled: June 14, 2007Date of Patent: March 29, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Steven D. Millman, Michael J. Torla
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Patent number: 7542567Abstract: One embodiment relates to a data processing system having a cryptographic unit. The cryptographic unit includes cryptographic circuitry which performs a first cryptographic function to provide security for a portion of the cryptographic unit, and which performs a second cryptographic function to provide security for a portion of the data processing system external to the cryptographic unit. The cryptographic unit may therefore operate in a normal operating mode and in a secure operating mode. During a first secure operating mode a first key is used to decrypt first security configuration information which includes a second key. During a second secure operating mode, the second key is used to decrypt second security configuration information. The cryptographic unit may include a secure internal memory such that during the secure operating modes, the cryptographic unit may only process descriptors provided from this secure internal memory.Type: GrantFiled: June 10, 2004Date of Patent: June 2, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Michael J. Torla, Thomas E. Tkacik
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Publication number: 20090022307Abstract: A technique for producing a hashed output of an input message according to any number of hash algorithms (e.g. SHA-256, SHA-348, SHA-512) having varying bit widths is described. At least a portion of the input message is stored in a first group of registers each having a bit width equal to a first bit width (e.g. 32 bits). If the selected hash algorithm has a larger bit width (e.g. 64 bits), a remainder of the input message is stored in a second plurality of registers each having a bit width equal to the first bit width. The hashed output is then computed according to the selected hash algorithm.Type: ApplicationFiled: July 20, 2007Publication date: January 22, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Michael J. Torla
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Publication number: 20080313397Abstract: A result value, such as a parity value, for a set of corresponding data elements from a plurality of storage devices is determined using a commutative operation. When accessing the set of corresponding data elements from a plurality of storage devices, a dual access can be performed for the storage device accessed last for the set of corresponding data elements so as to also obtain a data element from the last-accessed storage device for the next parity calculation. As a result, the number of storage device accesses can be reduced compared to conventional systems whereby a single access is performed for each storage device to obtain a single data element from the storage device.Type: ApplicationFiled: June 14, 2007Publication date: December 18, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Steven D. Millman, Michael J. Torla
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Patent number: 7142669Abstract: A Message Digest Hardware Accelerator (MDHA) 10 for implementing multiple cryptographic hash algorithms such as the Secure Hashing Algorithm 1 (SHA-1), the Message Digest 4 (MD4) algorithm and the Message Digest 5 (MD5) algorithm. A register file (12) is initialized to different data values. A function circuit (22) performs logical operations based on the selected algorithm and provides a data value to a summing circuit (30) that is summed with mode dependent constant values selected from registers (34 and 36), round and step dependent data words generated by a register array block (32) to calculate the hash value for a text message stored in registers (100–115).Type: GrantFiled: November 29, 2000Date of Patent: November 28, 2006Assignee: Freescale Semiconductor, Inc.Inventors: James D. Dworkin, Michael J. Torla
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Patent number: 6671709Abstract: An integrated cryptographic system (24) executes a mathematical algorithm that computes equations for public-key cryptography. An arithmetic processor (22) receives data values stored in a temporary storage memory (14) and computes both the Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC) algorithms. Multiplication cells (270 and 280) have an INT/POLY terminal that selects a C-register (246) for computing RSA modular exponentiation or ECC elliptic curve point multiplication.Type: GrantFiled: March 25, 2002Date of Patent: December 30, 2003Assignee: Motorola, Inc.Inventors: Philipp Michael Glaser, Michael J. Torla
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Publication number: 20030009503Abstract: An integrated cryptographic system (24) executes a mathematical algorithm that computes equations for public-key cryptography. An arithmetic processor (22) receives data values stored in a temporary storage memory (14) and computes both the Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC) algorithms. Multiplication cells (270 and 280) have an INT/POLY terminal that selects a C-register (246) for computing RSA modular exponentiation or ECC elliptic curve point multiplication.Type: ApplicationFiled: March 25, 2002Publication date: January 9, 2003Inventors: Philipp Michael Glaser, Michael J. Torla
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Publication number: 20020066014Abstract: A Message Digest Hardware Accelerator (MDHA) 10 for implementing multiple cryptographic hash algorithms such as the Secure Hashing Algorithm 1 (SHA-1), the Message Digest 4 (MD4) algorithm and the Message Digest 5 (MD5) algorithm. A register file (12) is initialized to different data values. A function circuit (22) performs logical operations based on the selected algorithm and provides a data value to a summing circuit (30) that is summed with mode dependent constant values selected from registers (34 and 36), round and step dependent data words generated by a register array block (32) to calculate the hash value for a text message stored in registers (100-115).Type: ApplicationFiled: November 29, 2000Publication date: May 30, 2002Applicant: Motorola, Inc.Inventors: James D. Dworkin, Michael J. Torla
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Patent number: 6397241Abstract: An integrated cryptographic system (24) executes a mathematical algorithm that computes equations for public-key cryptography. An arithmetic processor (22) receives data values stored in a temporary storage memory (14) and computes both the Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC) algorithms. Multiplication cells (270 and 280) have an INT/POLY terminal that selects a C-register (246) for computing RSA modular exponentiation or ECC elliptic curve point multiplication.Type: GrantFiled: December 18, 1998Date of Patent: May 28, 2002Assignee: Motorola, Inc.Inventors: Philipp Michael Glaser, Michael J. Torla
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Patent number: 6356636Abstract: A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in an adder (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value. The co-processor (44) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.Type: GrantFiled: July 22, 1998Date of Patent: March 12, 2002Assignee: Motorola, Inc.Inventors: Robert I. Foster, John Michael Buss, Rodney C. Tesch, James Douglas Dworkin, Michael J. Torla
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Patent number: 6182104Abstract: A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in a summer (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value. The co-processor (44) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.Type: GrantFiled: July 22, 1998Date of Patent: January 30, 2001Assignee: Motorola, Inc.Inventors: Robert I. Foster, John Michael Buss, Rodney C. Tesch, James Douglas Dworkin, Michael J. Torla