Abstract: A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface.

Abstract: Methods for imparting a texture to a cured powder coated surface are provided. These methods involve heating the cured powder coating to a temperature greater than its glass transition point (Tg), then imparting a texture to the cured powder coating under pressure using a release medium having a replicative surface. After the texture is imparted to the cured powder coating, the release medium can be removed. Examples of suitable release media include, for example, engraved plates, engraved rolls, release papers, release films, and release webs.

Abstract: Methods for imparting a texture to a cured powder coated surface are provided. These methods involve heating the cured powder coating to a temperature greater than its glass transition point (Tg), then imparting a texture to the cured powder coating under pressure using a release medium having a replicative surface. After the texture is imparted to the cured powder coating, the release medium can be removed. Examples of suitable release media include, for example, engraved plates, engraved rolls, release papers, release films, and release webs.

Abstract: Methods for applying and curing powder coatings, and for imparting a surface effect, e.g., texture or smoothness, to powder coated surfaces are provided. Preferred methods include pressing a textured release medium against the uncured powder coating and then curing the coating to form a thermally stable powder coating surface with the negative image of the texture on the release medium on its surface.

Abstract: A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

Abstract: Methods for applying and curing powder coatings, and for imparting a surface effect, e.g., texture or smoothness, to powder coated surfaces are provided. Preferred methods include pressing a textured release medium against the uncured powder coating and then curing the coating to form a thermally stable powder coating surface with the negative image of the texture on the release medium on its surface.

Abstract: A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

Abstract: A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

Abstract: A testing mode is provided for self testing of the transmitter and receiver pair provided on-chip. The testing mode targets each module individually; wherein when one of the two devices is placed under test, the other is used as a tester. When the transmitter is the device under test and the receiver is the tester that receives a transmitted signal from the transmitter, the receiver is used to determine the data eye size with the transmitted signal. When the receiver is the device under test and the transmitter is the tester, the transmitter is used to determine the amount of noise and power loss tolerated by the receiver.

Abstract: A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

Abstract: An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.

Abstract: An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.

Abstract: A testing mode is provided for self testing of the transmitter and receiver pair provided on-chip. The testing mode targets each module individually; wherein when one of the two devices is placed under test, the other is used as a tester. When the transmitter is the device under test and the receiver is the tester that receives a transmitted signal from the transmitter, the receiver is used to determine the data eye size with the transmitted signal. When the receiver is the device under test and the transmitter is the tester, the transmitter is used to determine the amount of noise and power loss tolerated by the receiver.

Abstract: Method and apparatus provides for testing a device or system with a pattern generator. A series of predetermined test vectors are stored, and, for at least some of the test vectors, an associated predetermined MISR signature. A test vector is applied to a device or system under test and a gold unit in response to a gating signal, the test vector having an associated MISR determined by simulating the expected result vector. In response thereto, the gold unit and the device or system under test each produce a result vector which are compared to detect errors in the performance of the system or device under test. A MISR signature is generated for the result vector from the gold unit. The MISR signature for the result vector is then compared to the MISR associated with the input test vector. If the signatures do not match, further test vectors are prevented from being applied to the device or system under test.

Abstract: An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.

Abstract: An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.