Abstract: There is disclosed, for use in a data processing device containing a master processor and a slave processor, a mode selection circuit capable of selecting the operating mode of the slave processor. The mode selection circuit comprises a mode determination circuit capable of determining the current operating mode of the master processor and a mode control circuit capable of causing the slave processor to operate in a selected operating mode in response to the current operating mode of the master processor. The mode selection circuit causes the slave processor to boot up to a test program stored in a ROM coupled to the slave processor whenever the master processor is in a test mode. If the master processor is in a system application mode, the mode selection circuit causes the slave processor to execute a system application program stored in a RAM coupled to the slave processor.

Abstract: There is disclosed, for use in a processing network containing a first node operable to transmit and receive frame relay data and a second node operable to transmit and receive asynchronous transfer mode (ATM) data, a network interface for converting the frame relay data to ATM data comprising: 1) a frame relay interface circuit operable to receive the frame relay data from the first node; 2) an ATM interface circuit operable to transmit the ATM data to the second node; 3) a data bus for coupling the frame relay interface circuit and the ATM interface circuit, the data bus operable to transfer frame payload data from the frame relay interface circuit to the ATM interface circuit; 4) a data traffic controller operable to receive frame header data from the frame relay interface circuit and control transfers of the frame payload data from the frame relay interface circuit to the ATM interface circuit; and 5) a bridge for coupling the data traffic controller to the data bus, the bridge isolating the data traffic