Patents by Inventor Michael J. Westphal
Michael J. Westphal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8324069Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.Type: GrantFiled: May 31, 2011Date of Patent: December 4, 2012Assignee: IXYS CH GmbHInventors: Timothy K. Carns, John L. Horvath, Lee J. DeBruler, Michael J. Westphal
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Patent number: 8093121Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.Type: GrantFiled: September 29, 2011Date of Patent: January 10, 2012Assignee: IXYS CH GmbHInventors: John A. Ransom, Brett D. Lowe, Michael J. Westphal
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Patent number: 8062941Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.Type: GrantFiled: April 2, 2011Date of Patent: November 22, 2011Assignee: IXYS CH GmbHInventors: John A. Ransom, Brett D. Lowe, Michael J. Westphal
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Patent number: 8017475Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.Type: GrantFiled: July 20, 2010Date of Patent: September 13, 2011Assignee: IXYS CH GmbHInventors: Timothy K. Carns, John L. Horvath, Lee J. DeBruler, Michael J. Westphal
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Patent number: 7927944Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.Type: GrantFiled: September 10, 2010Date of Patent: April 19, 2011Assignee: IXYS CH GmbHInventors: John A. Ransom, Brett D. Lowe, Michael J. Westphal
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Patent number: 7807528Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.Type: GrantFiled: March 24, 2009Date of Patent: October 5, 2010Assignee: ZiLOG, Inc.Inventors: John A. Ransom, Brett D. Lowe, Michael J. Westphal
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Patent number: 7768052Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.Type: GrantFiled: November 29, 2005Date of Patent: August 3, 2010Assignee: ZiLOG, Inc.Inventors: Timothy K. Carns, John L. Horvath, Lee J. DeBruler, Michael J. Westphal
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Patent number: 7601586Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.Type: GrantFiled: December 12, 2006Date of Patent: October 13, 2009Assignee: Micron Technology, Inc.Inventors: Ann K. Liao, Michael J. Westphal
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Patent number: 7508038Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.Type: GrantFiled: April 29, 2005Date of Patent: March 24, 2009Assignee: ZiLOG, Inc.Inventors: John A. Ransom, Brett D. Lowe, Michael J. Westphal
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Patent number: 7148102Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.Type: GrantFiled: September 1, 2005Date of Patent: December 12, 2006Assignee: Micron Technology, Inc.Inventors: Ann K. Liao, Michael J. Westphal
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Patent number: 7060584Abstract: A method of fabricating a high performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used. In the preferred embodiment, this is of the Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) type, although other Anti-Reflective Coatings (ARCs) or layers, such as a conductive film like TiN may be employed. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. In one embodiment, a Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.Type: GrantFiled: July 12, 1999Date of Patent: June 13, 2006Assignee: ZiLOG, Inc.Inventors: Timothy K. Carns, John L. Horvath, Lee J. DeBruler, Michael J. Westphal
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Patent number: 6939761Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.Type: GrantFiled: November 22, 2002Date of Patent: September 6, 2005Assignee: Micron Technology, Inc.Inventors: Ann K. Liao, Michael J. Westphal
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Patent number: 6831403Abstract: Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.Type: GrantFiled: December 20, 2002Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Kanwal K. Raina, Michael J. Westphal
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Publication number: 20040102027Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.Type: ApplicationFiled: November 22, 2002Publication date: May 27, 2004Inventors: Ann K. Liao, Michael J. Westphal
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Publication number: 20030094892Abstract: Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.Type: ApplicationFiled: December 20, 2002Publication date: May 22, 2003Applicant: Micron Technology, Inc.Inventors: Behnam Moradi, Kanwal K. Raina, Michael J. Westphal
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Patent number: 6509686Abstract: Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.Type: GrantFiled: September 16, 1999Date of Patent: January 21, 2003Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Kanwal K. Raina, Michael J. Westphal
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Patent number: 6362038Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.Type: GrantFiled: May 1, 2000Date of Patent: March 26, 2002Assignee: Micron Technology, Inc.Inventors: John K. Lee, Behnam Moradi, Michael J. Westphal
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Patent number: 6096589Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.Type: GrantFiled: February 12, 1998Date of Patent: August 1, 2000Assignee: Micron Technology, Inc.Inventors: John K. Lee, Behnam Moradi, Michael J. Westphal
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Patent number: 6015323Abstract: Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.Type: GrantFiled: January 3, 1997Date of Patent: January 18, 2000Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Kanwal K. Raina, Michael J. Westphal
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Patent number: 5945969Abstract: An anode of a field emission display has a substrate, a conductive layer, and one or more conductive members kept at a potential higher than the conductive layer to increase the component of the electric field normal to the surface of the anode at corners and edges of the anode so that the brightness across the display is more uniform than it would be without the conductive members.Type: GrantFiled: August 14, 1996Date of Patent: August 31, 1999Assignee: Micron Technology, Inc.Inventor: Michael J. Westphal