Patents by Inventor Michael J. Wiznerowicz

Michael J. Wiznerowicz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM-ON-CHIP SECURE DEBUG
    Publication number: 20150331043
    Abstract: A system on chip (SOC) includes a policy generator to identify lifecycle data that identifies a lifecycle of the SOC and identify authentication data that identifies a particular user that is to debug the SoC. A particular policy is determined based on the lifecycle and identification of the particular user, and policy data is sent to at least one block of the SoC, the policy data identifying the particular policy. Debug access at the block is based on the particular policy.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 19, 2015
    Inventors: Manoj R. Sastry, Enrico D. Carrieri, Michael Neve de Mevergnies, Ioannis T. Schoinas, Michael J. Wiznerowicz
  • Providing an on-die logic analyzer (ODLA) having reduced communications
    Patent number: 8745455
    Abstract: In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Ruben Ramirez, Michael J. Wiznerowicz, Sean T. Baartmans, Jason G. Sandri
  • Providing An On-Die Logic Analyzer (ODLA) Having Reduced Communications
    Publication number: 20120131404
    Abstract: In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 24, 2012
    Inventors: Ruben Ramirez, Michael J. Wiznerowicz, Sean T. Baartmans, Jason G. Sandri