Abstract: An integrated circuit device which implements a plurality of programmable digital logic functions derived from a number of digital logic inputs and further includes an on-chip digital-to-analog converter providing an analog output current signal responsive to the programmable logic functions derived from the digital inputs is provided. The means for implementing the programmable logic functions may include a programmable logic circuit having a programmable AND array comprising a plurality of AND gates, each with a plurality of inputs and at least one output. The AND gate inputs are selectively programmable with the input terms to generate an output signal to the AND gate outputs. The device further includes an OR gate array having a plurality of OR gates, each of the OR gates including a plurality of inputs and an output, thereby providing a plurality of OR gate array outputs generating a plurality of digital logic signals.

Abstract: A configurable logic array, includes a plurality of configurable logic cells which include a tristate output buffer, having an input receiving a logic signal from within the configurable logic cell, an output connected to the configurable interconnect structure and an output enable input. A plurality of selectors, controlled by the configuration memory, supply output enable signals for controlling corresponding tristate output buffers. The inputs to the plurality of selectors include a "common output enable signal," and at least a second logic signal, such as a constant high or constant low logic level. A circuit responsive to program data in the configuration memory and input signals from the interconnect structure generates the common output enable signal. One input of the selector is provided by an invertor connected from the input of the tristate output buffer to the selector for connecting an output signal to a long line in a wired-AND configuration.

Abstract: A single integrated circuit including programmable logic having a plurality of inputs and a plurality of outputs, with at least one input of the programmable logic coupled to an on-chip analog comparator is provided. In one aspect of the invention, a voltage comparator having programmable hysteresis for setting the output state switching thresholds of the comparator is utilized. In another aspect of the invention, the programmable logic comprises a programmable combinatorial array having a programmable AND array and a fixed OR array. The integrated circuit further comprises an output block including a plurality of flip-flops and output buffers coupled to at least one I/O pin for selectively determining the state of the I/O pin. In yet another aspect the invention, the programmable combinatorial array includes a plurality of AND array outputs, divided into three subsets, for input to three pairs of OR gates which comprise the fixed OR plane of the device.

Abstract: A high density segmented programmable array logic device utilizes a switch interconnection matrix to couple an array of programmable logic cells. Each programmable logic cell includes programmable input logic macrocells, programmable feedback logic macrocells, programmable output logic macrocells, buried state logic macrocells and an assembly of programmable AND gates and OR gates. Each input macrocell, output macrocell and buried state macrocell has means for generating either a registered/latched output signal or a combinatorial output signal in response to an input signal to the cell. The various switches are used to couple signals to or from the assembly of programmable AND gates and OR gates.

Abstract: A real-time database provides the predictable, high speed data access required for on-line applications, while providing flexible searching capabilities. The data retrieval routines include the option to "read-through-lock" to access data in locked data tables, the capability to directly access to data using tuple identifiers, and the capability to directly access unformatted data from input areas which contain blocks of unformatted data. The data updating routines include an option to omit index updating when updating data and an option to update data in a locked data table. Multiple indexes can be defined for a data table. Thus, high speed searches can be performed based on a variety of data fields. The data storage and retrieval mechanisms are independent and there are hash index tables that connect the multiple index keys to the data tables. The data table structure includes a column defined for storing tuple identifier strings.

Abstract: The excitation winding of an alternator is energized through a silicon controlled rectifier (SCR) from the output of the alternator. The SCR is bypassed by a constant current network to allow the alternator to start up; even with no excitation current, when the alternator output voltage is due to residual magnetism alone, this network can pass a current into the excitation winding, and build the current up gradually to a value above the latching current of the SCR. When this has happened, the SCR can latch on after being fired, and takes over control of the excitation current. Because the network is a constant-current network rather than a purely resistive network, it can be designed to pass sufficient current at low alternator output voltages, without having to dissipate excessive power at higher output voltages. Also, when the output voltage is at its normal operating value, the constant-current network is rendered non-conductive, to avoid the excessive power dissipation which might occur at full voltage.

Abstract: The excitation winding of an alternator is energized through a silicon controlled rectifier (SCR) from the output of the alternator. The SCR is bypassed by a constant current network to allow the alternator to start up; even with no excitation current, when the alternator output voltage is due to residual magnetism alone, this network can pass a current into the excitation winding, and build the current up gradually to a value above the latching current of the SCR. When this has happened, the SCR can latch on after being fired, and takes over control of the excitation current. Because the network is a constant-current network rather than a purely resistive network, it can be designed to pass sufficient current at low alternator output voltages, without having to dissipate excessive power at higher output voltages. Also, when the output voltage is at its normal operating value, the constant-current network is rendered non-conductive, to avoid the excessive power dissipation which might occur at full voltage.