Patents by Inventor Michael J. Zierak

Michael J. Zierak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250142860
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a gate structure; a first barrier layer under and adjacent to the gate structure; and a second barrier layer over the first barrier layer and which is adjacent to the gate structure.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 1, 2025
    Inventors: Steven J. Bentley, Santosh Sharma, Johnatan A. Kantarovsky, Mark D. Levy, Michael J. Zierak
  • Patent number: 12278178
    Abstract: An integrated circuit (IC) structure includes a transistor in a device layer over a substrate, the transistor including a gate; and a plurality of interconnect layers over the device layer, the plurality of interconnect layers including a last metal layer. A process-induced damage (PID) protection structure includes a conductor coupling the gate to a well in the substrate but includes an open fuse element therein. A first metal interconnect extends from a first terminal of the open fuse element to a first pad in the last metal layer, and a second metal interconnect extending from a second terminal of the open fuse element to a second pad in the last metal layer. The fuse element is closed during fabrication, and the metal interconnects allow opening of the fuse element to deactivate the PID protection structure after fabrication.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 15, 2025
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Michael J. Hauser, Michael J. Zierak
  • Publication number: 20250120155
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a semiconductor substrate; at least one insulator film over the semiconductor substrate, the at least one insulator film including a recess; and a field plate extending into the at least one recess and over the at least one insulator film.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Inventors: Mark D. Levy, Johnatan A. Kantarovsky, Michael J. Zierak, Santosh Sharma, Steven J. Bentley
  • Publication number: 20250089284
    Abstract: A structure according to the disclosure includes a dielectric layer over a substrate and horizontally between a gate terminal and a source/drain (S/D) terminal. The dielectric layer has a first surface proximal to the substrate and a second surface opposite the first surface. The dielectric layer has a plurality of recesses in the second surface. At least some of the plurality of recesses have different depths. A conductive field plate includes a metal layer on the second surface and within the plurality of recesses. The conductive field plate is electrically isolated from the gate terminal and the S/D terminal.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Inventors: Johnatan Avraham Kantarovsky, Michael J. Zierak, Santosh Sharma, Mark D. Levy, Steven J. Bentley
  • Publication number: 20250040221
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; a first field plate on a first side of the gate structure; and a second field plate on a second side of the gate structure, independent from the first field plate.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Inventors: Johnatan A. KANTAROVSKY, Mark D. LEVY, Alvin J. JOSEPH, Santosh SHARMA, Michael J. ZIERAK
  • Patent number: 12154956
    Abstract: Disclosed are a structure with a multi-level field plate and a method of forming the structure. The field plate includes multiple first conductors on a dielectric layer and separated from each other by spaces with different widths (e.g., by with progressively decreasing widths). A conformal additional dielectric layer extends over the first conductors and onto the dielectric layer within the spaces. The field plate also includes, on the additional dielectric layer, second conductor(s) with portions thereof extending into the spaces. Within the spaces, the second conductor portions are at different heights (e.g., at progressively increasing heights) above the dielectric layer. Such a field plate can be incorporated into a transistor (e.g., a high electron mobility transistor (HEMT)) to, not only reduce the peak of an electric field exhibited proximal to a gate terminal, but to ensure the electric field is essentially uniform level between the gate and drain terminals.
    Type: Grant
    Filed: April 11, 2024
    Date of Patent: November 26, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Johnatan Avraham Kantarovsky, Rajendran Krishnasamy, Mark D. Levy, John J. Ellis-Monaghan, Michael J. Zierak, Kristin Marie Welch
  • Patent number: 12028053
    Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: July 2, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Steven M. Shank, Yves T. Ngu, Michael J. Zierak, Siva P. Adusumilli
  • Publication number: 20240194680
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bidirectional device, methods of manufacture and methods of operation. The structure includes: a first gate structure adjacent to a first source region; a second gate structure adjacent to a second source region; and field plates adjacent to the first gate structure, the second gate structure and a surface of an active layer of the first gate structure and the second gate structure.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 13, 2024
    Inventors: Santosh SHARMA, Michael J. ZIERAK, Mark D. LEVY, Steven J. BENTLEY
  • Publication number: 20240186384
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor (HEMT) and methods of manufacture. The structure includes: a gate structure; a source contact and a drain contact adjacent to the gate structure; and a field plate electrically isolated from the gate structure and abutting the source contact and the drain contact.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Inventors: Santosh SHARMA, Michael J. ZIERAK, Steven J. BENTLEY, Mark D. LEVY
  • Patent number: 11972999
    Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: April 30, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Mark D. Levy, Rajendran Krishnasamy, Michael J. Zierak, Siva P. Adusumilli
  • Publication number: 20240128328
    Abstract: The present disclosure relates to a structure which includes at least one gate structure over semiconductor material, the at least one gate structure comprising an active layer, a gate metal extending from the active layer and a sidewall spacer on sidewalls of the gate metal, and a field plate aligned with the at least one gate structure and isolated from the gate metal by the sidewall spacer.
    Type: Application
    Filed: October 12, 2022
    Publication date: April 18, 2024
    Inventors: Michael J. ZIERAK, Steven J. BENTLEY, Santosh SHARMA, Mark D. LEVY, Johnatan A. KANTAROVSKY
  • Publication number: 20240105595
    Abstract: Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Johnatan A. Kantarovsky, Santosh Sharma, Michael J. Zierak, Steven J. Bentley, Ephrem G. Gebreselasie
  • Publication number: 20240085247
    Abstract: A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Santosh Sharma, Michael J. Zierak, Steven J. Bentley, Johnatan Avraham Kantarovsky
  • Publication number: 20240006309
    Abstract: An integrated circuit (IC) structure includes a transistor in a device layer over a substrate, the transistor including a gate; and a plurality of interconnect layers over the device layer, the plurality of interconnect layers including a last metal layer. A process-induced damage (PID) protection structure includes a conductor coupling the gate to a well in the substrate but includes an open fuse element therein. A first metal interconnect extends from a first terminal of the open fuse element to a first pad in the last metal layer, and a second metal interconnect extending from a second terminal of the open fuse element to a second pad in the last metal layer. The fuse element is closed during fabrication, and the metal interconnects allow opening of the fuse element to deactivate the PID protection structure after fabrication.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Michael J. Hauser, Michael J. Zierak
  • Patent number: 11764060
    Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: September 19, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Michel J. Abou-Khalil, Steven M. Shank, Alvin J. Joseph, Michael J. Zierak
  • Publication number: 20230223425
    Abstract: Embodiments of the disclosure provide a method, including forming a shallow trench isolation (STI) in a substrate. The method further includes doping the substrate with a noble dopant, thereby forming a disordered crystallographic layer under the STI. The method also includes converting the disordered crystallographic layer to a doped buried polysilicon layer under the STI and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The method includes forming a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer.
    Type: Application
    Filed: March 23, 2023
    Publication date: July 13, 2023
    Inventors: Michael J. Zierak, Siva P. Adusumilli, Yves T. Ngu, Steven M. Shank
  • Publication number: 20230188131
    Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: Steven M. Shank, Yves T. Ngu, Michael J. Zierak, Siva P. Adusumilli
  • Publication number: 20230178449
    Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 8, 2023
    Inventors: Mark D. Levy, Rajendran Krishnasamy, Michael J. Zierak, Siva P. Adusumilli
  • Patent number: 11664412
    Abstract: A structure provides a polysilicon resistor under a shallow trench isolation (STI). The structure includes the STI, a resistor in the form of a doped buried polysilicon layer under the STI, and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The structure also includes a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer. A related method is also disclosed.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: May 30, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Michael J. Zierak, Siva P. Adusumilli, Yves T. Ngu, Steven M. Shank
  • Patent number: 11637173
    Abstract: A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 25, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Yves T. Ngu, Siva P. Adusumilli, Steven M. Shank, Michael J. Zierak, Mickey H. Yu