Patents by Inventor Michael James Becht
Michael James Becht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12681832Abstract: A trace assist unit operable with a plurality of processor cores is described. The trace assist unit comprises a plurality of physical buffers, and loading circuitry and unloading circuitry that are communicatively coupled with the plurality of physical buffers. The loading circuitry receives trace events from various ones of the plurality of processor cores, each of the trace events having a respective category from a plurality of predefined categories. The loading circuitry writes the trace events to respective ones of the plurality of physical buffers that are assigned to the respective categories of the plurality of predefined categories. The loading circuitry transmits, responsive to one or more predefined conditions, an unload signal to the unloading circuitry to unload contents of a selected physical buffer of the plurality of physical buffers to an external memory.Type: GrantFiled: July 28, 2023Date of Patent: July 14, 2026Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Howard Michael Haynie, Raymond Wong, Deepankar Bhattacharjee, Michael James Becht, Luke Hopkins, Subhasis Samanta
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Publication number: 20260180913Abstract: A method for recovering requests on bus protocol buffers within a network switch without disturbing data flow is disclosed. A register with multiple entries is provided within a network switch. Each entry of the register includes a LCHID. The entries of the LCHIDs within the register that need recovery can be set, for example, via a mask. A request in the network switch includes a source ID field for storing LCHID information of the request. After converting the request's LCHID information to a “one-hot” format, the request's LCHID information is then compared to the entries of LCHIDs within the register. The request is marked as a bad LCHID request if there is a match, and recovery will be suppressed for a Denied Response that is sent to a controller within the network switch. The bad LCHID request will then be cleaned up while allowing other requests to go to their respective destinations such that data flow of the network switch is not disturbed.Type: ApplicationFiled: December 23, 2024Publication date: June 25, 2026Applicant: International Business Machines CorporationInventors: Aditi Desai, Michael James Becht, Luke Hopkins
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Publication number: 20260169920Abstract: Adapter snooping in hardware using a split structure cache includes: receiving, by a hardware snooping module, a completion packet from a network adapter, storing, by the hardware snooping module, a data structure associated with the completion packet in a split structure cache included within the hardware snooping module, performing, by the hardware snooping module, a hardware snoop on the data structure, including updating the data structure based on the completion packet, where the hardware snooping module is configured to determine whether to interrupt firmware based on the hardware snoop of the data structure, and sending, by the hardware snooping module, the updated data structure to system memory.Type: ApplicationFiled: December 16, 2024Publication date: June 18, 2026Inventors: DEEPANKAR BHATTACHARJEE, GIRISH GOPALA KURUP, HOWARD MICHAEL HAYNIE, MICHAEL JAMES BECHT, SUBHASIS SAMANTA
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Patent number: 12657139Abstract: Embodiments herein describe assigning requests from hardware modules that are transmitted by a shared interconnect to destinations (e.g., workers) in the same integrated circuit (IC) into groups. For example, the destinations can be assigned into respective groups. When a request is received, a group classifier can use the destination address in the request to identify its group. The request can be stored in a request buffer, while the location of the request in the request buffer is stored in a group buffer. Each hardware module can include a request buffer and a group buffer for each group in the system.Type: GrantFiled: June 5, 2023Date of Patent: June 16, 2026Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael James Becht, Aditi Desai
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Patent number: 12650943Abstract: A method, system, and program product are provided. Based on feature tag, which I/O adapters access same endpoint for each source/destination pair are identified. I/O adapter utilization statistics are continuously monitored based on feature tag demand for each of a plurality of feature tag groups. Based on detecting I/O adapter utilization statistics for a feature tag group being above a configurable threshold value, dynamically reconfiguring the I/O adapters by feature tag across path groups, whereby an underutilized I/O adapter is removed from the feature tag group being above the configurable threshold value and added to an overutilized feature tag group.Type: GrantFiled: June 14, 2024Date of Patent: June 9, 2026Assignee: International Business Machines CorporationInventors: Michael James Becht, Pasquale A. Catalano, Christopher J Colonna
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Patent number: 12613819Abstract: Methods, systems, and products for system steering for an I/O sustainability target includes tracking, for each adapter of a plurality of adapters included in a system, a power consumption associated with the adapter and an amount of data transferred by the adapter, calculating, based on the tracking, a power to data ratio associated with the plurality of adapters, and routing one or more I/O commands to a lowest power adapter of the plurality of adapters based on comparing the power to data ratio with a power target.Type: GrantFiled: May 15, 2024Date of Patent: April 28, 2026Assignee: International Business Machines CorporationInventors: Michael James Becht, Pasquale A. Catalano, Christopher J Colonna
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Publication number: 20260111360Abstract: Method and apparatus for memory location prediction in a distributed memory system are provided. A memory access request is received from a requesting device, the memory access request comprising a target address. A tracking table is checked to determine that data corresponding to the target address is stored in a remote memory, where the remote memory comprises one or more memory modules. In response to the determination, a search is initiated in the remote memory to identify a memory module that contains the data corresponding to the target address prior to completing a search in a local memory. The identified data is received from the identified memory module in the remote memory. The tracking table is updated with an entry corresponding to the target address.Type: ApplicationFiled: October 22, 2024Publication date: April 23, 2026Inventors: Craig R. WALTERS, Yamil A. RIVERA, Matthias KLEIN, Michael James BECHT
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Patent number: 12585474Abstract: The embodiments herein describe techniques for implementing enhanced boot processing of an embedded compute complex including a plurality of cores. Disclosed embodiments enable isolating the plurality of cores of the embedded compute complex from other components of a computing system when the cores are released from reset at the beginning of the boot initialization sequence, and enable a hierarchical boot process for booting the plurality of cores of the embedded compute complex.Type: GrantFiled: March 11, 2024Date of Patent: March 24, 2026Assignee: International Business Machines CorporationInventors: Luke Hopkins, Michael James Becht, Ying-Yeung Li, Clinton E. Bubb
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Patent number: 12556524Abstract: A receiving network device of a network obtains a command built to enable a control program of a device coupled to the receiving network device to provide to the receiving network device status of a key manager. The receiving network device obtains the status from the command and uses the status in performing one or more actions.Type: GrantFiled: August 28, 2023Date of Patent: February 17, 2026Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pasquale A. Catalano, Michael James Becht, Christopher J Colonna, Stephen Robert Guendert
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Publication number: 20250384004Abstract: A method, system, and program product are provided. Based on feature tag, which I/O adapters access same endpoint for each source/destination pair are identified. I/O adapter utilization statistics are continuously monitored based on feature tag demand for each of a plurality of feature tag groups. Based on detecting I/O adapter utilization statistics for a feature tag group being above a configurable threshold value, dynamically reconfiguring the I/O adapters by feature tag across path groups, whereby an underutilized I/O adapter is removed from the feature tag group being above the configurable threshold value and added to an overutilized feature tag group.Type: ApplicationFiled: June 14, 2024Publication date: December 18, 2025Inventors: Michael James Becht, Pasquale A. Catalano, Christopher J Colonna
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Patent number: 12487651Abstract: A receiving network device obtains a command built to enable a control program of a device coupled to the receiving network device to obtain power consumption data of one or more selected units of a network. The command includes an indication of the one or more selected units for which the power consumption data is to be obtained. The receiving network device obtains the power consumption data of the one or more selected units indicated by the command and provides a response to the request for the power consumption data of the one or more selected units.Type: GrantFiled: August 28, 2023Date of Patent: December 2, 2025Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pasquale A. Catalano, Michael James Becht, Christopher J Colonna, Stephen Robert Guendert
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Publication number: 20250355820Abstract: Methods, systems, and products for system steering for an I/O sustainability target includes tracking, for each adapter of a plurality of adapters included in a system, a power consumption associated with the adapter and an amount of data transferred by the adapter, calculating, based on the tracking, a power to data ratio associated with the plurality of adapters, and routing one or more I/O commands to a lowest power adapter of the plurality of adapters based on comparing the power to data ratio with a power target.Type: ApplicationFiled: May 15, 2024Publication date: November 20, 2025Inventors: MICHAEL JAMES BECHT, PASQUALE A. CATALANO, CHRISTOPHER J COLONNA
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Patent number: 12461867Abstract: A method, computer system, and a computer program product for sustainable data storage is provided. An IOP discovers a path between each defined I/O adapter and its endpoint. Based on a system configuration and the discovered pathing, the IOP builds a table comprising each I/O adapter, endpoint, initial adapter state. The IOP creates an I/O adapter redundancy mapping from the table and assign performance thresholds to each I/O adapter. The IOP continuously monitors utilization of each I/O adapter, whereby based on utilization for the I/O adapter reaching a defined threshold, the IOP enables a redundant I/O adapter path, whereby the redundant I/O adapter is a proxy for the I/O adapter.Type: GrantFiled: June 24, 2024Date of Patent: November 4, 2025Assignee: International Business Machines CorporationInventors: Michael James Becht, Pasquale A. Catalano, Christopher J Colonna
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Publication number: 20250321906Abstract: Feature management for I/O adapters includes receiving an instruction for an I/O operation, the instruction including a feature tag indicating a feature related to an I/O adapter capability; and routing, based on the feature tag and information describing a plurality of I/O adapters, the I/O operation to an I/O adapter enabled with the feature.Type: ApplicationFiled: April 16, 2024Publication date: October 16, 2025Inventors: MICHAEL JAMES BECHT, PASQUALE A. CATALANO, CHRISTOPHER J COLONNA
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Publication number: 20250284501Abstract: The embodiments herein describe techniques for implementing enhanced boot processing of an embedded compute complex including a plurality of cores. Disclosed embodiments enable isolating the plurality of cores of the embedded compute complex from other components of a computing system when the cores are released from reset at the beginning of the boot initialization sequence, and enable a hierarchical boot process for booting the plurality of cores of the embedded compute complex.Type: ApplicationFiled: March 11, 2024Publication date: September 11, 2025Inventors: Luke HOPKINS, Michael James BECHT, Ying-Yeung LI, Clinton E. BUBB
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Patent number: 12379742Abstract: Embodiments of the present disclosure implement hardware-based snoop logic streaming timers for input/output (I/O) communications between a host and a shared network adapter in a computing system. The disclosed embodiments describe a hardware-based snoop logic and snoop logic timer function control of input/output (I/O) processor monitoring a defined memory area to detect a completion queue entry being written to a completion queue, and implementing streaming timers and interpacket timers, based on the completion queue entry and predefined configuration information for an associated host interface connection, to provide streaming data status, interpacket arrival times, and streaming timer expiration for the associated host interface connection.Type: GrantFiled: January 26, 2024Date of Patent: August 5, 2025Assignee: International Business Machines CorporationInventors: Howard Michael Haynie, Michael James Becht, Dan Vangor, Bruce Ratcliff, Girish Gopala Kurup, Mushfiq Us Saleheen, Deepankar Bhattacharjee
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Publication number: 20250244787Abstract: Embodiments of the present disclosure implement hardware-based snoop logic streaming timers for input/output (I/O) communications between a host and a shared network adapter in a computing system. The disclosed embodiments describe a hardware-based snoop logic and snoop logic timer function control of input/output (I/O) processor monitoring a defined memory area to detect a completion queue entry being written to a completion queue, and implementing streaming timers and interpacket timers, based on the completion queue entry and predefined configuration information for an associated host interface connection, to provide streaming data status, interpacket arrival times, and streaming timer expiration for the associated host interface connection.Type: ApplicationFiled: January 26, 2024Publication date: July 31, 2025Inventors: Howard Michael HAYNIE, Michael James BECHT, Dan VANGOR, Bruce RATCLIFF, Girish Gopala KURUP, Mushfiq Us SALEHEEN, Deepankar BHATTACHARJEE
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Patent number: 12346276Abstract: A port speed of a port of a device is automatically set. A command is obtained at the device. The command provides an indication of a target port of the device and a selected port speed. Based on obtaining the command and using the device, a port speed of the target port is automatically set to the selected port speed.Type: GrantFiled: May 18, 2023Date of Patent: July 1, 2025Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pasquale A. Catalano, Christopher J Colonna, Stephen Robert Guendert, Michael James Becht
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Patent number: 12320843Abstract: Systems and techniques for performing processor debugging over an internal interconnect fabric are described. An example techniques includes obtaining interconnect fabric traffic comprising one or more debugging commands for a first processor within a computing system. The interconnect fabric traffic with the one or more debugging commands is converted into debugging traffic with the one or more debugging commands. The debugging traffic is routed to a debug port of the first processor.Type: GrantFiled: August 31, 2023Date of Patent: June 3, 2025Assignee: International Business Machines CorporationInventors: Michael James Becht, Clinton E. Bubb
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Publication number: 20250139009Abstract: Systems and techniques for snooping input/output (I/O) events in a computing system are described. An example technique includes obtaining a configuration comprising a plurality of snoop space profiles, each snoop space profile indicating a respective range of memory addresses that map to a respective completion queue. The technique also includes monitoring input/output (I/O) traffic exchanged across a communication interface between an I/O adapter and a processor in a computing system, based on the configuration. The technique further includes performing one or more actions to assist processing of the I/O traffic, based in part on the monitoring.Type: ApplicationFiled: October 31, 2023Publication date: May 1, 2025Inventors: Howard Michael HAYNIE, Michael James BECHT, Mushfiq Us SALEHEEN, Dan VANGOR, Girish Gopala KURUP, Luke HOPKINS, Bruce RATCLIFF