Abstract: An electronic cigarette apparatus including a first and second modules; the first removably connected to the second; wherein the first module includes a male connector, a tank, and an upper portion; wherein the second module includes a lower portion which removably connects to the upper portion of the first module to removably connect the first and second modules; and wherein the second module further includes a female connector and a battery device. The lower portion may include a top section having at least two tabs; and wherein the upper portion includes at least two slots into which the at least two tabs of the lower portion can be inserted to connect the upper and lower portions. The upper portion may include one or more ledges which assist in preventing the lower and upper portions from disconnecting, unless the upper portion is rotated with respect to the lower portion.

Abstract: Described embodiments provide a server for transferring data packets of streaming data sessions between devices. The server includes an accelerator that, for received data packets, i) extracts header fields of the packets, ii) determines, based on the header fields, a destination for the packets, and iii) provides the packets to the destination. For data to be transmitted, the accelerator i) groups the data into packets, ii) generates header fields for the packets, and iii) provides the packets to the network. A memory arbiter manages accesses to memory that buffers data and stores keys corresponding to the data sessions. A storage medium stores media files corresponding to the data sessions. A key manager includes i) a first memory for storing a master key of the server, ii) a second memory for storing one or more keys corresponding to the data sessions, and iii) a processor to encrypt and decrypt data.

Abstract: A bidirectional bus repeater is disclosed that connects individual segments of a bidirectional bus. The exemplary bidirectional bus repeater consists of a direction control block and a buffer block. The buffer block contains one pair of buffers for each bus bit and an extra pair associated with the indicator lines. Indicator lines are used by the direction control block based on activity on the bus to generate control signals (control-A and control-B) that control the state of the tri-state buffers. In an exemplary embodiment, each node must toggle the indicator line whenever the node drives the bus. When the bus is inactive, the control-A and control-B signals generated by the direction control block are both inactive because the voltages on both sides of the bidirectional bus repeater are the same. When the direction control block detects a change of voltage on the indicator line associated with one side of the bus (e.g., indicator-A associated with bus-A), the corresponding tri-state buffers are enabled.

Abstract: A bidirectional bus repeater is disclosed that connects individual segments of a bidirectional bus. The exemplary bidirectional bus repeater consists of a direction control block and a buffer block. The buffer block contains one pair of buffers for each bus bit and an extra pair associated with the indicator lines. Indicator lines are used by the direction control block based on activity on the bus to generate control signals (control-A and control-B) that control the state of the tri-state buffers. In an exemplary embodiment, each node must toggle the indicator line whenever the node drives the bus. When the bus is inactive, the control-A and control-B signals generated by the direction control block are both inactive because the voltages on both sides of the bidirectional bus repeater are the same. When the direction control block detects a change of voltage on the indicator line associated with one side of the bus (e.g., indicator-A associated with bus-A), the corresponding tri-state buffers are enabled.

Abstract: A clock switch controller has a clock status register which stores current clock data which identifies which of two or more clock signal sources is a current clock signal source currently in use as a system clock signal source. State machine logic of the controller automatically switches, in response to a clock switch signal, the system clock signal source from the current clock signal source to a new clock signal source of the two or more clock signal sources.

Abstract: An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions.