Patents by Inventor Michael James Manfra

Michael James Manfra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149262
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Application
    Filed: December 23, 2021
    Publication date: May 12, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra
  • Patent number: 11211543
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: December 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra
  • Patent number: 11201273
    Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 14, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dmitry Igorevich Pikulin, Geoffrey Charles Gardner, Raymond Leonard Kallaher, Georg Wolfgang Winkler, Sergei Vyatcheslavovich Gronin, Peter Krogstrup Jeppesen, Michael James Manfra, Andrey Antipov, Roman Mykolayovych Lutchyn
  • Publication number: 20210375623
    Abstract: The present disclosure relates to a method of manufacturing a nanowire structure. According to an exemplary process, a substrate is firstly provided. An intact buffer region is formed over the substrate, and a sacrificial top portion of the intact buffer region is eliminated to provide a buffer layer with a planarized top surface. Herein, the planarized top surface has a vertical roughness below 10 ?. Next, a patterned mask with an opening is formed over the buffer layer, such that a portion of the planarized top surface of the buffer layer is exposed. A nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask. The buffer layer is configured to have a lattice constant that provides a transition between the lattice constant of the substrate and the lattice constant of the nanowire.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Geoffrey C. GARDNER, Sergei V. GRONIN, Raymond L. KALLAHER, Michael James MANFRA
  • Publication number: 20210375624
    Abstract: The present disclosure relates to a nanowire structure, which includes a substrate with a substrate body and an ion implantation region, a patterned mask with an opening over the substrate, and a nanowire. Herein, the substrate body is formed of a conducting material, and the ion implantation region that extends from a top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the substrate body is exposed through the opening of the patterned mask, while the ion implantation region is fully covered by the patterned mask. The nanowire is directly formed over the exposed surface portion of the substrate body and is not in contact with the ion implantation region. Furthermore, the nanowire is confined within the ion implantation region, such that the ion implantation region is configured to provide a conductivity barrier of the nanowire in the substrate.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Geoffrey C. GARDNER, Sergei V. GRONIN, Raymond L. KALLAHER, Michael James MANFRA
  • Patent number: 11127820
    Abstract: A quantum well field-effect transistor (QWFET) includes a barrier layer, a quantum well layer, and a spacer layer. The quantum well layer is on the barrier layer. The barrier layer and the spacer layer comprise aluminum indium antimonide that is undoped. The quantum well layer comprises indium antimonide. The spacer layer is on the quantum well layer. The quantum well layer and the spacer layer are between a source contact and a drain contact. A gate contact is on a dielectric layer, which is on the spacer layer. By providing the barrier layer and the spacer layer as undoped layers, a performance of the QWFET may be improved.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 21, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Michael James Manfra, Candice Fanny Thomas
  • Publication number: 20210280763
    Abstract: A semiconductor-superconductor hybrid structure includes a semiconductor layer and a superconductor heterostructure on the semiconductor layer. The superconductor heterostructure includes a first superconductor layer on the semiconductor layer and a second superconductor layer on the first superconductor layer. The first superconductor layer comprises a first superconducting material and the second superconductor layer comprises a second superconducting material that is different from the first superconducting material. By providing the superconductor heterostructure as multiple layers of different superconducting materials, the superconducting and physical properties of the superconductor heterostructure can be improved compared to conventional superconducting homostructures, thereby increasing the performance of the semiconductor-superconductor hybrid structure.
    Type: Application
    Filed: December 23, 2019
    Publication date: September 9, 2021
    Inventors: Geoffrey C. GARDNER, Raymond L. KALLAHER, Sergei V. GRONIN, Michael James MANFRA
  • Publication number: 20210210599
    Abstract: A nanowire structure includes a substrate, a graded planar buffer layer, a patterned mask, and a nanowire. The graded planar buffer layer is on the substrate. The patterned mask is on the graded planar buffer layer and includes an opening through which the graded planar buffer layer is exposed. The nanowire is on the graded planar buffer layer in the opening of the patterned mask. A lattice constant of the graded planar buffer layer is between a lattice constant of the substrate and a lattice constant of the nanowire. By providing the graded planar buffer layer, lattice mismatch between the nanowire and the substrate can be reduced or eliminated, thereby improving the quality and performance of the nanowire structure.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 8, 2021
    Inventors: Geoffrey C. GARDNER, Sergei V. GRONIN, Raymond L. KALLAHER, Michael James MANFRA
  • Publication number: 20210175408
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Application
    Filed: February 20, 2020
    Publication date: June 10, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra
  • Publication number: 20210126181
    Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor, a superconductor, and a barrier between the superconductor and the semiconductor. The device is configured to enable energy level hybridisation between the semiconductor and the superconductor. The barrier is configured to increase a topological gap of the device. The barrier allows for control over the degree of hybridisation between the semiconductor and the superconductor. Further aspects provide a quantum computer comprising the device, a method of manufacturing the device, and a method of inducing topological behaviour in the device.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Georg Wolfgang Winkler, Roman Mykolayovych Lutchyn, Geoffrey Charles Gardner, Raymond Leonard Kallaher, Sergei Vyatcheslavovich Gronin, Michael James Manfra, Farhad Karimi
  • Publication number: 20210091294
    Abstract: A hybrid heterostructure includes a semiconductor layer comprising indium antimonide, a superconductor layer comprising aluminum, and a screening layer between the semiconductor layer and the superconductor layer, the screening layer comprising indium arsenide. By including a screening layer of indium arsenide between the semiconductor layer of indium antimonide and the superconductor layer of aluminum, a high-performance and durable hybrid heterostructure suitable for use in quantum computing devices is provided.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Inventors: Candice Fanny THOMAS, Michael James MANFRA
  • Publication number: 20210091185
    Abstract: A quantum well field-effect transistor (QWFET) includes a barrier layer, a quantum well layer, and a spacer layer. The quantum well layer is on the barrier layer. The barrier layer and the spacer layer comprise aluminum indium antimonide that is undoped. The quantum well layer comprises indium antimonide. The spacer layer is on the quantum well layer. The quantum well layer and the spacer layer are between a source contact and a drain contact. A gate contact is on a dielectric layer, which is on the spacer layer. By providing the barrier layer and the spacer layer as undoped layers, a performance of the QWFET may be improved.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Inventors: Michael James MANFRA, Candice Fanny THOMAS
  • Publication number: 20210083166
    Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 18, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Dmitry Igorevich Pikulin, Geoffrey Charles Gardner, Raymond Leonard Kallaher, Georg Wolfgang Winkler, Sergei Vyatcheslavovich Gronin, Peter Krogstrup Jeppesen, Michael James Manfra, Andrey Antipov, Roman Mykolayovych Lutchyn
  • Patent number: 7038300
    Abstract: An apparatus includes a crystalline substrate having a top surface, a crystalline semiconductor layer located on the top surface, and a plurality of dielectric regions. The crystalline semiconductor layer includes group III-nitride and has first and second surfaces. The first surface is in contact with the top surface. The second surface is separated from the top surface by semiconductor of the crystalline semiconductor layer. The dielectric regions are located on the second surface. Each dielectric region is distant from the other dielectric regions and covers an end of an associated lattice defect. Each lattice defect threads the crystalline semiconductor layer.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: May 2, 2006
    Assignee: Lucent Technologies Inc.
    Inventors: Julia Wang-Ping Hsu, Michael James Manfra
  • Patent number: 7001813
    Abstract: One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. The two-step growth produces a lower density of threading defects.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: February 21, 2006
    Assignee: Lucent Technologies Inc.
    Inventors: Michael James Manfra, Nils Guenter Weimann
  • Publication number: 20040124427
    Abstract: An apparatus includes a crystalline substrate having a top surface, a crystalline semiconductor layer located on the top surface, and a plurality of dielectric regions. The crystalline semiconductor layer includes group III-nitride and has first and second surfaces. The first surface is in contact with the top surface. The second surface is separated from the top surface by semiconductor of the crystalline semiconductor layer. The dielectric regions are located on the second surface. Each dielectric region is distant from the other dielectric regions and covers an end of an associated lattice defect. Each lattice defect threads the crystalline semiconductor layer.
    Type: Application
    Filed: December 12, 2003
    Publication date: July 1, 2004
    Inventors: Julia Wan-Ping Hsu, Michael James Manfra, Nils Guenter Weimann
  • Patent number: 6699760
    Abstract: One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. The two-step growth produces a lower density of threading defects. Another method includes epitaxially growing a layer of group III-nitride semiconductor on a lattice-mismatched crystalline substrate and then, chemically treating a growth surface of the layer to selectively electrically passivate defects that thread the layer.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: March 2, 2004
    Assignee: Lucent Technologies, Inc.
    Inventors: Julia Wan-Ping Hsu, Michael James Manfra, Nils Guenter Weimann
  • Publication number: 20030235970
    Abstract: One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. The two-step growth produces a lower density of threading defects.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 25, 2003
    Inventors: Julia Wan-Ping Hsu, Michael James Manfra, Nils Guenter Weimann
  • Publication number: 20030235934
    Abstract: One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. The two-step growth produces a lower density of threading defects.
    Type: Application
    Filed: January 22, 2003
    Publication date: December 25, 2003
    Inventors: Michael James Manfra, Nils Guenter Weimann
  • Patent number: 6349454
    Abstract: A thin film resonator (TFR) is produced with an improved piezoelectric film which is epitaxially grown on a growing surface, resulting in a piezoelectric film with less grain boundaries. Epitaxial growth refers to the piezoelectric film having a crystallographic orientation take from or emulating the crystallographic orientation of a single crystal substrate or growing surface. For example, by epitaxially growing a piezoelectric film on a single crystal silicon substrate as the growing surface, an improved piezoelectric film is produced with little or no grain boundaries. Also provided is a method of making a TFR in which the piezoelectric film is grown on a substrate. Subsequently, a portion of the substrate is removed, and the electrodes are deposited on either side of the piezoelectric film.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: February 26, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Michael James Manfra, Loren Neil Pfeiffer, Kenneth William West, Yiu-Huen Wong