Abstract: An anti jitter circuit for reducing time jitter in an input pulse train comprises an integrator, a DC removal circuit and a comparator. The anti jitter circuit also has a feedback loop effective to suppress phase deviation of the output pulse train in response to jitter.

Abstract: An anti-jitter circuit has an integrator storage capacitor. A charge pump derives from an input pulse train at least one charge packet during each cycle of the input pulse train and supplies the charge packets to the storage capacitor. A controlled current sink operating in conjunction with a high impedance low pass filter continuously discharges the storage capacitor to create a sawtooth voltage waveform having a mean d.c. voltage level. A differential comparator compares the sawtooth voltage waveform with the mean d.c.

Abstract: A noise reduction circuit useful as a clock restoration circuit includes a DC removal circuit for removing a DC level from an input pulse train, an integrator for integrating the input pulse train after a DC level has been removed, a comparator for comparing the integrator output with a threshold value (Vmp) to detect for a missing pulse, a pulse generator inserting into the input pulse train an additional pulse delayed with respect to any missing pulse, and an output circuit for generating an output pulse train from the integrator output.

Abstract: A phase noise reduction circuit for reducing phase noise in an input pulse train consisting of pulses which are all of the same length and which, in the absence of phase noise, have a nominal frequency f, includes a DC removal circuit for removing a DC level from the input pulse train, an integrator for integrating the input pulse train after a DC level has been removed therefrom by the DC removal circuit and a comparator for deriving from the integrated pulse train an output pulse train containing periodic transitions at said nominal frequency. The input pulse train may be derived using a monostable circuit.

Abstract: A frequency synthesizer of the phase lock loop type including a reference frequency source, a voltage-controlled oscillator and a frequency divider connected to the oscillator output to divide the output frequency by a selectively-variable integer N. The outputs of the frequency divider and the reference frequency source are applied to a phase comparator which has an output connected to a filter. The filter output is applied through a multiplier, having a multiplication factor n proportional to N, to the input of the voltage controlled oscillator. The frequency divider and the multiplier are controlled by the same control means in order to keep the loop gain constant, irrespective of the amount of change in N.

Abstract: A phase comparator indicating a phase difference range of n .times. 360.degree., between two input signals, comprising edge triggered shift registers, for dividing the input signals by n, means for modulating the width of the resulting output pulses in proportion to the phase difference of the input signals, and integrating means to combine the modulated pulses into a time-averaged signal which is indicative of the phase difference.